104
HCD-FR10W
Pin No.
Pin Name
I/O
Description
62
PHREFO
O
Bit clock signal (2.8224 MHz) output to the digital audio processor Not used
63
ZDFL
O
Front L-ch Zero data flag detection signal output terminal Not used
64
DSAL
O
Front L-ch DSD data output to the digital audio processor
65
ZDFR
O
Front R-ch Zero data flag detection signal output terminal Not used
66
DSAR
O
Front R-ch DSD data output to the digital audio processor
67
VDDSD0
—
Power supply terminal (+3.3V) (for DSD data output)
68
ZDFC
O
Center zero data flag detection signal output terminal Not used
69
DSAC
O
Center DSD data output to the digital audio processor
70
ZDFLFE
O
Woofer zero data flag detection signal output terminal Not used
71
DSALFE
O
Woofer DSD data output to the digital audio processor
72
VSDSD1
—
Ground terminal (for DSD data output)
73
ZDFLS
O
Rear L-ch zero data flag detection signal output terminal Not used
74
DSALS
O
Rear L-ch DSD data output to the digital audio processor
75
ZDFRS
O
Rear R-ch zero data flag detection signal output terminal Not used
76
DSARS
O
Rear R-ch DSD data output to the digital audio processor
77
VDDSD
—
Power supply terminal (+3.3V) (For DSD data output)
78, 79
IOUT0, IOUT1
O
Data output terminal for IEEE 1394 link chip interface Not used
80
VSCB0
—
Ground terminal (for core)
81, 82
IOUT2, IOUT3
O
Data output terminal for IEEE 1394 link chip interface Not used
83
VDCB0
—
Power supply terminal (+2.5V) (for core)
84, 85
IOUT4, IOUT5
O
Data output terminal for IEEE 1394 link chip interface Not used
86
VSIOB0
—
Ground terminal (for I/O)
87
IANCO
O
Transmission information data output terminal for IEEE 1394 link chip interface
Not used
88
IFULL
I
Data transmission hold request signal input terminal for IEEE 1394 link chip
interface Not used
89
IEMPTY
I
High speed transmission request signal input terminal for IEEE 1394 link chip
interface Not used
90
VDIOB0
—
Power supply terminal (+3.3V) (for I/O)
Frame reference signal output terminal for IEEE 1394 link chip interface Not used
Enable signal output terminal for IEEE 1394 link chip interface Not used
Data transmission clock signal output terminal for IEEE 1394 link chip interface
Not used
Ground terminal (for core)
I
Not used
I
Not used
I
Not used
Not used
99
VDCB1
—
Power supply terminal (+2.5V) (for core)
100
IVLD
I
Not used
101 to 105
IDIN0 to IDIN4
I
Not used
106
VSIOB1
—
Ground terminal (for I/O)
107 to 109
IDIN5 to IDIN7
I
Not used
110
VDIOB1
—
Power supply terminal (+3.3V) (for I/O)
111 to 114
WAD0 to WAD3
I
External A/D data input terminal for PSP physical disc mark detection Not used
115
TESTI
I
Input terminal for the test (normally: fixed at “L”)
116
VSCB2
—
Ground terminal (for core)
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