Sony DTV-01, Manual

Page: 116 / 132

119
P M 3 3 9 4 , F L U K E & P H I L I P S
c h 4
c h 3
c h 2
c h 1
c h 1 : f r e q = 3 1 . 5 k H z
c h 3 : d c = 1 1 7 V
C H 1 ! 1 0 . 0 V =
C H 2 ! 5 0 . 0 V =
C H 3 ! 5 0 . 0 V =
C H 4 ! 1 0 . 0 V = C H P M T B 1 0 . 0 u s c h 1 -
1
2
3
4
T
W a v e fo rm D fb – W id e 1 6 :9 a s p e c t r a tio p ic tu r e
N a m e L o c a t io n V o lta g e
C h a n n e l 1 D F - V C N 1 3 0 3 /p in 1 1 2 V p - p
C h a n n e l 2 A m p lifie d D F - V Q 7 0 0 9 /D 1 3 5 V p - p
C h a n n e l 3 B + t o D F T T 7 0 0 1 / p in 1 1 7 1 V d c
C h a n n e l 4 D F - D e t C N 1 3 0 3 /p in 2 7 V p - p
T im e b a s e 1 0 u s e c /d iv
Current and Voltage Amplification
The pulse manufactured by comparator IC1502/pin 14 is buffered by Q1501
and Q1510. It leaves the M board through fusible resistor R1504 at CN1303/
pin 1 as the DF-V signal (ch 2).
On the D board, this pulse is amplified and inverted by Q7009. Q7009’s
source is rec135Vdc supply voltage that leaves from its drain lead
when turned on (conducting).
As with any MOSFET, when the voltage at its gate is kept at the source
potential, the MOSFET is OFF (no D-S current). As the gate voltage is
brought towards the drain potential, the MOSFET begins to conduct. Un-
like a transistor, conduction begins when the gate voltage is about 2-4
volts.
Therefore when the DF-V pulse brings the gate voltage low, Q7009 con-
ducts, passing the +135Vdc from its source to the drain. The input volt-
age of only 12Vp-p at Q7009’s gate is amplified to 135Vp-p at its drain.
The signal is also inverted. This signal is low pass filtered into a DC volt-
age by L7003 and C7032. The resultant DC voltage is applied to T7001/
pin 11. D7010 at Q7009’s Drain lead prevents a negative voltage there.
The negative voltage is caused by the collapsing field of the resonate tank
circuit connected to the drain lead.
D C V o lt a g e O u tp u t t o D F T T 7 0 0 1 /p in 1 1
M o d e A s p e c t R a tio D C V o lt a g e
N o r m a l 4 :3 7 1 V
Z o o m , F u ll, C C , H D T V r e c e p tio n . 1 6 :9 1 1 7 V
Regulation
A sample of the dynamic focus voltage from DFT T7001/pin 4 (and the
FBT pulse) is returned to the first pulse manufacturing stage at IC1502/pin
8 for regulation. C7019 and C7020 couples the DFT T7001/pin 14 signal
on the D board to become the DF-Det signal (ch 4).
The DF-DET signal is then rectified by D1502 on the M board before being
buffered by Q1503, inverted by IC1503, and returned to IC1502/pin 8 for
fine pulse width correction. These changes to the static focus voltage will
also result in corresponding changes to the dynamic focus voltage.
R e g u l a t i o n V o l t a g e s
M o d e D F - D E T
C N 1 3 0 3 / 2
D 1 5 0 2 /
C a t h o d e
D 1 5 0 4 /
A n o d e
I C 1 5 0 3 /
P in 1 4
N o r m a l 4 : 3 7 V p - p 3 . 2 6 V 4 . 5 5 V 1 . 7 6 V
F u ll 1 0 V p - p 6 . 0 7 V 7 . 3 V 9 . 7 V
Z o o m 1 0 V p - p 6 . 0 7 V 7 . 3 V 9 . 7 V
H D T V 1 0 V p - p 6 . 0 7 V 7 . 3 V 9 . 7 V