Sony DTV-01, Manual

Page: 100 / 132

103
Summary
The regulation path that corrects for B+ variations can be shown in this
chart that begins with an increased load that reduces the B+:
R e g u la t io n f o r I n c r e a s e d L o a d
P W M B +
Q 4 0 2 2 / D
E r r o r o u t
I C 4 0 1 1 / 6
A m p
I C 4 0 0 5 / 7
P u ls e
I C 4 0 0 4 / 1
P u ls e
Q 4 0 2 2 / G
O u t p u t
Q 4 0 2 2 / D
D C is W id t h is W id t h is
lo w e r N a r r o w e r N a r r o w e r
A positive gate pulse is used to turn OFF the P channel PWM output de-
vice (Q4022) so the narrower the pulse, the higher the B+ voltage.
PWM Output Circuit
This output circuit consists of a buffer (Q4015 and Q4014) which is used
to supply drive current to the gate of Q4022. An inverted pulse is output at
Q4022’s drain and applied through FBT T7002 to the horizontal output
transistor Q4018 collector. This PWM voltage serves as the regulated B+
voltage for Q4018.