Sony DMP-1000P, Service Manual, Page: 54 / 79

5-57
Confidential
DMP-1000P (AEP)
Pin No. Pin Name I/O Description
55 VSS — Ground terminal
56 CS O Chip select signal output terminal Not used (open)
57 FLASH O Chip select signal output to the flash memory (IC506) “L” active
58 XACK O Acknowledge signal output terminal Not used
59 FDC DMA ACK O DMA acknowledge signal output to the floppy disk drive controller (IC2101)
60 STB I Strobe signal input terminal Not used
61 VSS — Ground terminal
62 IR-DRQ — Not used (open)
63 VCC — Power supply terminal (+5V)
64 MAC-HSKI I HSKI input terminal Not used
65 CD I Control signal input terminal Not used (fixed at “H”)
66 IR-IRQ I Not used (fixed at “L”)
67 VBLK I V blanking signal input from the A/D, D/A converter (IC407) “L” active
68 XSTB I Strobe signal input terminal Not used
69 RESET FDC O
Reset signal output to the floppy disk drive controller (IC2101) “L”: reset
70 R/B I
R/B select signal input terminal Not used (open)
71 VSS —
Ground terminal
72 FDD READY OUT O
Ready signal output to the floppy disk drive controller (IC2101) and floppy disk drive unit
73 to 76 D15 to D12 I/O
Two-way data bus with the A/D, D/A converter (IC407), mechanism controller (IC505) and
D-RAM (IC509) (upper 8 bit)
77 VCC —
Power supply terminal (+5V)
78 D11 I/O
Two-way data bus with the A/D, D/A converter (IC407), mechanism controller (IC505) and
D-RAM (IC509) (upper 8 bit)
79 VSS —
Ground terminal
80 to 82 D10 to D8 I/O
Two-way data bus with the A/D, D/A converter (IC407), mechanism controller (IC505) and
D-RAM (IC509) (upper 8 bit)
83, 84 D7, D6 I/O
Two-way data bus with the A/D, D/A converter (IC407), mechanism controller (IC505), flash
memory (IC506), D-RAM (IC509) and floppy disk drive controller (IC2101) (lower 8 bit)
85 VCC —
Power supply terminal (+5V)
86 D5 I/O
Two-way data bus with the A/D, D/A converter (IC407), mechanism controller (IC505), flash
memory (IC506), D-RAM (IC509) and floppy disk drive controller (IC2101) (lower 8 bit)
87 VSS —
Ground terminal
88 to 92 D4 to D0 I/O
Two-way data bus with the A/D, D/A converter (IC407), mechanism controller (IC505), flash
memory (IC506), D-RAM (IC509) and floppy disk drive controller (IC2101) (lower 8 bit)
93 VSS —
Ground terminal
94 XTL I
System clock input terminal (7.159 MHz)
95 MD3 I
Setting terminal for the CPU operational mode (fixed at “H” in this set)
96 EXTL O
System clock output terminal (7.159 MHz)
97 MD2 I
Setting terminal for the CPU operational mode (fixed at “L” in this set)
98 XINIT I
Interrupt input terminal Not used (fixed at “L”)
99 VCC/FWP O
Control signal output for the EEPROM communication bus
100 RESET/WP O
Wakeup control signal output terminal Not used (open)
101 XWAIT I
Wait control input from the A/D, D/A converter (IC407) “L” active
102 MD1/BOOT I
Setting terminal for the CPU operational mode (fixed at “H” in this set)
103 MD0 I
Setting terminal for the CPU operational mode (fixed at “L” in this set)
104 PLL VCC —
Power supply terminal (+5V) (PLL system)
105 PLL CAP I
Connected to capacitor for the PLL