Sony CX-JV1, Service Manual

Page: 58 / 98

58
CX-JV1
•
VMP50 BOARD IC802 ES3889 (MPEG VIDEO/AUDIO DECODER)
Pin No. Pin Name I/O Description
1, 2 GND —
Ground terminal
3 NC —
Not used
4, 5 VDD — Power supply terminal (+5V)
6 DSC-C I
Clock signal input from the video CD MPEG processor
7 AUX00 I
Video system select switch input terminal “L”: PAL, “H”: AUTO or NTSC
8 DSCD0 I/O Two-way data bus with the video CD MPEG processor Data input from the program ROM
9 AUX01 I
Video system select switch input terminal “L”: NTSC, “H”: PAL or AUTO
10 DSC-C I
Strobe signal input from the video CD MPEG processor
11 AUX02 O Serial data load output to the D/A converter
12 DCLK O
System clock signal output to the video CD MPEG processor
13 RST I
Reset signal input terminal “L”: reset
14 AUX07 I
Internal status (SENSE) signal input from the digital signal processor
15 MUTE O
Audio muting on/off control signal output terminal Not used
16 VDD —
Power supply terminal (+5V)
17 MCLK I
Audio master clock signal input from the video CD MPEG processor
18 AUX08 O Laser diode on/off control signal output to the RF amplifier “L”: laser diode on
19 TWS I
Audio frame sync signal input from the video CD MPEG processor
20 AUX09 I/O
Subcode Q data input from the video CD MPEG processor
21 TSD I Audio data input from the video CD MPEG processor
22 TBCK I
Audio bit clock signal (2.8224 MHz) input from the video CD MPEG processor
23 PWS/SPLL1 I/O
Audio frame sync signal output to the video CD MPEG processor
Selection signal input terminal for the PLL clock frequency of the DCLK (pin
qs
) output
(fixed at “H” in this set)
24 RSTOUT O Reset signal output to the video CD MPEG processor “L”: reset
25, 26 GND —
Ground terminal
27, 28 NC —
Not used
29 to 31 GND — Ground terminal
32 VDD —
Power supply terminal (+5V)
33 RSD/SPLL0 I/O
Audio data output to the video CD MPEG processor
Selection signal input terminal for the PLL clock frequency of the DCLK (pin
qs
) output
(fixed at “L” in this set)
34 AUX10 O
Reading clock signal output to the digital signal processor
35 AUX11 I Interrupt request signal input from the video CD MPEG processor
36 AUX12 I
C2 pointer signal input from the digital signal processor
37 RBCK/SER IN I/O
Audio bit clock signal (2.8224 MHz) output to the video CD MPEG processor
Selection signal input terminal for the serial input DSC mode
“L”: parallel DSC mode, “H”: serial DSC mode (fixed at “L” in this set)
38 AUX13 O Reset signal output to the digital signal processor and motor/coil driver “L”: reset
39 AUX14 I
Subcode sync (S0+S1) detection signal input from the digital signal processor
40
AUX15
I
Serial data input from the system controller
41 AGND — Ground terminal (analog system)
42 VREFM I
Not used
43 VREFP I
Not used
44 AVDD —
Power supply terminal (+5V) (analog system)
45 AOR+ O
Audio data (R-ch) output to the electrical volume
46 AOR– O
Audio data (R-ch) output to the electrical volume
47 AOL+ O
Audio data (L-ch) output to the electrical volume