Sony CX-JV1, Service Manual

Page: 56 / 98

56
CX-JV1
•
VMP50 BOARD IC801 ES3880FM (VIDEO CD MPEG PROCESSOR)
Pin No. Pin Name I/O Description
1 VDD3 —
Power supply terminal (+3.3V)
2 RAS O
Row address strobe signal output to the D-RAM
3 DWE O Write enable signal output to the D-RAM
4 to 12 MA0 to MA8 O
Address signal output to the D-RAM
13 to 28
DBUS0 to
DBUAS15
I/O Two-way data bus with the D-RAM
29 RESET I Reset signal input from the MPEG video/audio decoder “L”: reset
30 GND —
Ground terminal
31 VDD3 —
Power supply terminal (+3.3V)
32 to 39 YUV0 to YUV7 O YUV 8-bit video data bus output to the MPEG video/audio decoder
40 VSYNC I
Vertical sync signal input from the MPEG video/audio decoder “L”: active
41 HSYNC I
Horizontal sync signal input from the MPEG video/audio decoder “L”: active
42 DCLK I System clock signal input from the MPEG video/audio decoder
43
PCLK2X
I
27 MHz pixel clock signal input from the MPEG video/audio decoder
44
PCLK
I
13.5 MHz pixel clock signal input from the MPEG video/audio decoder
45 AUX0 I Guard frame sync signal input from the digital signal processor
46 AUX1 I
Focus OK signal input from the digital signal processor
47 CD ACK O Acknowledge signal input from the system controller
48 AUX3 O
Serial data transfer clock signal output to the digital signal processor
49 AUX4 O Interrupt request signal output to the MPEG video/audio decoder
50 GND —
Ground terminal
51 VDD3 —
Power supply terminal (+3.3V)
52 AUX6 O Strobe signal output to the system controller
53 AUX5 O
Strobe signal output to the MPEG video/audio decoder
54 AUX7 O Serial data output to the system controller
55 to 62 LD0 to LD7 I/O Two-way data bus with the MPEG video/audio decoder Data input from the program ROM
63 LWR O
Write enable signal output terminal Not used
64 LOE O
Output enable signal output to the program ROM
65 LCS3 O Chip enable signal output to the program ROM
66 LCS1 O
Clock signal output to the MPEG video/audio decoder
67 LCS0 O
Chip select signal output terminal Not used
68 to 79 LA12 to LA17 O Address signal output to the program ROM
80 GND —
Ground terminal
81 VDD5 —
Power supply terminal (+5V)
82 to 87 LA0 to LA11 O Address signal output to the program ROM
88 ACLK O
Master clock signal output to the MPEG video/audio decoder
89
AOUT/
SELPLL0
O
Audio data output to the MPEG video/audio decoder
Selection signal input terminal for the PLL clock frequency of the DCLK (IC802: pin
qs
) output
(fixed at “L” in this set)
90
ATCLK
O
Audio bit clock signal (2.8224 MHz) output to the MPEG video/audio decoder
91
ATPS/
SELPLL1
O
Audio frame sync signal output to the MPEG video/audio decoder
Selection signal input terminal for the PLL clock frequency of the DCLK (IC802: pin
qs
) output
(fixed at “L” in this set)
92 DOE O
Output enable signal output to the D-RAM
93 AIN I
Audio serial data input from the MPEG video/audio decoder
94 ARCLK I Audio bit clock signal (2.8224 MHz) input from the MPEG video/audio decoder
95 ARFS I
Audio frame sync signal input from the MPEG video/audio decoder