Sony CMOS CXP854P60 Specification Download Page 16

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CXP854P60

(6) I

C bus timing

(Ta = –10 to +75°C, V

= 4.5 to 5.5V, Vss = 0V)

Item

SCL clock frequency

Bus free time before starting transfer

Hold time for starting transfer

Clock low level width

Clock high level width

Set-up time for repeated transfers

Data hold time

Data set-up time

SDA, SCL rise time

SDA, SCL fall time

Set-up time for transfer completion

SLC

BUF

HD; STA

LOW

HIGH

SU; STA

HD; DAT

SU; DAT

SU; STO

SCL

SDA, SCL

SCL

SDA, SCL

4.7

4.0

4.7

4.0

4.7

∗

0.25

4.7

100

0.3

kHz

µs

Symbol

Condition

Min.

Max.

Unit

∗

Since SCL rise time (max: 300ns) is not considered part of data hold time, allow at least 300ns.

Fig. 9. I

C bus transfer data timing

SU; STO

SU; STA

HD; STA

SU; DAT

HIGH

HD; DAT

LOW

HD; STA

BUF

SDA

SCL

Fig. 10. I

C device suggested circuit

device

SDA0
(or SDA1)

SCL0
(or SCL1)

• A pull-up resistor must be connected to SDA0 (or SDA1), and SCL0 (or SCL1).

• The SDA0 (or SDA1) and SCL0 (or SCL1) series resistance (Rs = 300

Ω

or less) can be used to reduce spike

noise caused by CRT flashover.

Summary of Contents for CMOS CXP854P60

Page 1: ...t half blanking shadow background color on full screen Double scanning mode supported includes jitter elimination circuit I2C bus interface 14 bit PWM output 8 bit PWM output 8 channels Remote control receiver circuit 8 bit A D converter 4 channels 20µs conversion time 4MHz 8MHz HSYNC counter 2channels Watchdog timer 8 bit synchronized serial I O 8 bit timer 8 bit timer counter 19 bit time base ti...

Page 2: ...PORT A PORT B PORT C PORT D PORT E PORT F 2 2 V SS V DD MP RST XTAL EXTAL PD0 INT2 PE1 INT1 PE0 INT0 PF0 PWM0 to PF7 PWM7 INTERRUPT CONTROLLER PE6 PWM PA0 to PA7 PB0 to PB7 PC0 to PC7 PD0 to PD7 PE0 to PE5 PE6 to PE7 PF0 to PF7 XLC EXLC R G B I YS YM PA7 HSYNC PA6 VSYNC PD3 SI PD2 SO PD1 SCK PD7 EC PE7 TO PD6 RMC PD4 HS0 PD5 HS1 PE2 AN0 to PE5 AN3 PF4 SCL0 PF5 SCL1 PF6 SDA0 PF7 SDA1 HSYNC COUNTER ...

Page 3: ...5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 30 40 39 38 37 36 35 34 31 32 33 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 63 64 61 62 1 PA1 PA0 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 EC PD7 PF3 PWM3 PF4 PWM4 SCL0 PF5 PWM5 SCL1 PF6 PWM6 SDA0 PF7 PWM7 SDA1 YM YS I B G R EXLC XLC PE0 INT0 PE1 INT1 PE2 AN0 PE3 AN1 PE4 AN2 PE5 AN3 RMC PD6 H...

Page 4: ...SDA0 PF7 PWM7 SDA1 R G B I YS YM I O I O Input I O Input I O I O I O Input I O I O I O Output I O Input I O Input I O Input I O Input I O Input Input Input Input Input Output Output Output Output Output Output Output Output I O Output Output I O Output I O Function CRT display vertical synchronization signal input pin CRT display horizontal synchronization signal input pin Input pin for external i...

Page 5: ...external clock input to EXTAL pin and leave XTAL pin open L level active system reset This pin also acts as an I O pin during power up While internal power on reset function is talking place a L level is output Test mode input pin Must be connected to GND Positive power supply pin for incorporated PROM writing Under normal operating conditions connect to VDD Positive supply voltage pin GND Both Vs...

Page 6: ...on AAAA AAAA Port A data Input protection circuit AAAA Input multiplexer VSYNC HSYNC Data bus RD Port D AA AA IP AA AA AAAA AAAA Port D direction AAAA AAAA Port D data Large current source 12mA INT2 SI HS0 HS1 RMC EC Schmitt input Pin Equivalent I O Circuit Port A Port B Port C Port A Port D 22 lines 2 lines 6 lines Hi Z Hi Z Hi Z Pin When reset Circuit format PA0 to PA5 PB0 to PB7 PC0 to PC7 PA6 ...

Page 7: ... AAAA IP RD Port E Data bus Schmitt input To interrupt circuit AA AA AA AA IP Input multiplexer To A D converter RD Port E Data bus TO PWM AAAAA Port E selection AAAAA AA Port E data Port D Port E 2 lines 2 lines 4 lines 2 lines Pin When reset Circuit format PE0 INT0 PE1 INT1 Port E Port E Hi Z Hi Z Hi Z H level PE2 AN0 to PE5 AN3 PD1 SCK PD2 SO PE6 PWM PE7 TO ...

Page 8: ...ge torelance Large current source 12mA Port F Port F 4 lines 4 lines 6 lines 2 lines Pin When reset Circuit format PF4 PWM4 SCL0 PF5 PWM5 SCL1 PF6 PWM6 SDA0 PF7 PWM7 SDA1 Hi Z Hi Z Hi Z Oscillation halted R G B I YS YM PF0 PWM0 to PF3 PWM3 EXLC XLC AA AA R G B I YS YM To output polarity register Writing data to port register brings output from high impedance to active AAAA AAAA Output polarity Osc...

Page 9: ... Circuit format RST Oscillation L level EXTAL XTAL AA AA AA IP AA EXTAL XTAL Diagram indicates equivalent circuit during oscillation Feedback resistor is disconnected during STOP AA AA Schmitt input Pull up resistor From power on reset circuit ...

Page 10: ...PF3 Total of all output pins Excludes large current output Large current output 2 Total of all output pins SDIP QFP Item Symbol Ratings Unit Remarks Absolute Maximum Ratings Vss 0V Supply voltage High level input voltage Low level input voltage Operating temperature 5 5 5 5 5 5 VDD VDD VDD 0 3 0 3VDD 0 2VDD 0 4 75 V V V V V V V V V V C Item Symbol Min Max Unit Remarks 4 5 3 5 2 5 0 7VDD 0 8VDD VDD...

Page 11: ...A to PD PE6 PE7 R G B I YS YM PA to PD PE6 PE7 R G B I YS YM PF0 to PF3 RST PD PF PF4 to PF7 SCL0 SCL1 SDA0 SDA1 EXTAL RST PA to PE HSYNC VSYNC R G B I YS YM PF0 to PF3 PF4 to PF7 SCL0 SCL1 SDA0 SDA1 VDD 5 5V VIL 0 4V VDD 5 5V VI 0 5 5V VDD 5 5V VOH 12 0V VDD 5 5V VOH 5 5V VDD 4 5V VSCL0 VSCL1 2 25V VSDA0 VSDA1 2 25V VDD 1 Operating mode 1 2 clock rate 8MHz crystal oscillator C1 C2 22pF All output...

Page 12: ...ter input clock rise and fall times fC tXL tXH tCR tCF tEH tEL tER tEF XTAL EXTAL EXTAL EXTAL EC EC MHz ns ns ns ms Item System Pin Condition Min Max Unit Fig 1 Fig 2 Fig 1 Fig 2 External clock drive Fig 1 Fig 2 External clock drive Fig 3 Fig 3 3 5 50 tsys 50 9 200 20 Ta 10 to 75 C VDD 4 5 to 5 5V Vss 0V Fig 1 Clock timing EXTAL tXH tXL tCF tCR 0 4V VDD 0 4V 1 fc Fig 2 Clock applied condition AAAA...

Page 13: ...0 100 200 200 100 200 100 ns ns ns ns ns ns ns ns ns ns SCK SI SI SO tKH tKL tSIK tKSI tKSO SCK high and low level widths SI input set up time referenced to SCK SI input hold time referenced to SCK SCK SO delay time System Pin Condition Min Max Unit Note For SCK output mode in addition to output delay time SO capacitance must be 50pF 1TTL Fig 4 Serial transfer timing 0 2VDD 0 8VDD tKL tKH SO tKCY ...

Page 14: ...FF VDD Power on reset Repeated power on reset 0 05 1 50 ms ms Item Symbol Pin Condition Min Max Unit 3 Interrupt Reset input Ta 10 to 75 C VDD 4 5 to 5 5V Vss 0V 4 Power on reset Power on reset Ta 10 to 75 C VDD 4 5 to 5 5V Vss 0V 0 2VDD 0 8VDD tIH tIL INT0 to INT2 falling edge 0 2V 0 2V 4 5V VDD tR tOFF Take care when turning on power Fig 5 Interrupt input timing tRSL 0 2VDD RST Fig 6 RST input t...

Page 15: ... 10 to 75 C VDD 4 5 to 5 5V Vss 0V Linearity error VZT VFT Analog input FFH FEH 01H 00H Digital conversion value Fig 8 Definitions for A D converter terms 1 VZT Digital conversion values change between 00H 01H 2 VFT Digital conversion values change between 0EH 0FH 3 fADC indicates the below values due to the bit6 CKS of A D control registor address 00F6H and the Bit 7 PCK1 and Bit 6 PCK0 of clock ...

Page 16: ...CL SDA SCL SDA SCL SDA SCL SDA SCL 0 4 7 4 0 4 7 4 0 4 7 0 0 25 4 7 100 1 0 3 kHz µs µs µs µs µs µs µs µs µs µs Symbol Pin Condition Min Max Unit Since SCL rise time max 300ns is not considered part of data hold time allow at least 300ns Fig 9 I2C bus transfer data timing P St tSU STO tSU STA tHD STA tSU DAT tHIGH tHD DAT tF tR tLOW tHD STA S P tBUF SDA SCL Fig 10 I2C device suggested circuit I2C ...

Page 17: ...YNC Fig 12 Fig 11 Fig 11 Fig 11 4 1 2 7 1 14 2 200 1 0 4 1 2 MHz µs ns µs 11 1 16 2 200 1 0 Symbol Pin Condiiton Unit Shadow Existent Min Max Min Max Shadow Non existent 1 Oscillator clock at 4MHz operation 2 Oscillator clock at 8MHz operation Fig 11 OSD timing 0 8VDD 0 2VDD tHCG tHWD HSYNC For OPOL register 01FAH bit 7 at 0 0 8VDD 0 2VDD tVCG VSYNC For OPOL register 01FAH bit 6 at 0 Fig 12 LC osc...

Page 18: ...2 30 12 0 0 C1 pF C2 pF Rd Ω Circuit Example i ii i 27 27 0 i Indicates types with on chip grounding capacitors C1 and C2 Product List RIVER ELETEC CO LTD Option item Package Program ROM capacitance Reset pin pull up resistor Power on reset circuit Font data 64 pin plastic SDIP QFP 52K 60K byte Existent Non existent Existent Non existent User specified 64 pin plastic SDIP QFP PROM 60K byte Existen...

Page 19: ...0 100 C1 C2 Capacitance pF 5 0MHz 6 5MHz 13 0MHz VDD Supply voltage V I DD Supply current mA IDD vs VDD fc 8MHz Ta 25 C Typical fc System clock MHz IDD vs fc VDD 5V Ta 25 C Typical 1 2 frequency mode SLEEP mode 1 4 frequency mode 1 16 frequency mode 1 2 frequency mode 1 4 frequency mode 1 16 frequency mode SLEEP mode 20 16 14 12 10 I DD Supply current mA 18 fOSC C C1 C2 1 2π LC ...

Page 20: ...57 6 1 778 SOLDER PLATING 8 6g 0 3 0 3 0 to 15 PACKAGE STRUCTURE 64PIN SDIP PLASTIC MIN 0 5 MIN 3 0 4 75 0 1 0 9 0 15 0 5 0 1 0 25 0 05 0 1 17 1 0 1 19 05 1 32 33 64 1 778 57 6 0 1 0 4 PACKAGE MATERIAL LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN 42 COPPER ALLOY SONY CODE EIAJ CODE JEDEC CODE SDIP 64P 01 P SDIP64 17 1x57 6 1 778 SOLDER PLATING 8 6g 0 3 0 3 0 to 15 PACKAGE STRUCTURE LEAD S...

Page 21: ...LATING 42 COPPER ALLOY PACKAGE STRUCTURE 1 5g 1 0 0 to10 SONY CODE EIAJ CODE JEDEC CODE 23 9 0 4 20 0 0 1 0 4 0 1 0 15 14 0 0 1 1 19 20 32 33 51 52 64 0 15 0 05 0 1 2 75 0 15 16 3 0 1 0 05 0 2 0 8 0 2 M 0 2 0 15 0 4 17 9 0 4 0 4 0 35 64PIN QFP PLASTIC QFP 64P L01 P QFP64 14x20 1 0 PACKAGE MATERIAL LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER PLATING 42 COPPER ALLOY PACKAGE STRUCTUR...

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