48
Pin. No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46 to 48
49
50
51
52
53
54
55
Pin Name
PC1
PC2
DVSS
DVSS
LPS
LREQ
DVDD
SCLK
DVSS
CTL0
CTL1
DVDD
DATAO
DATA1
DVSS
DATA2
DATA3
DVDD
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVDD
DVDD
DVSS
PURB
AVDD
AVSS
AVDD
XO
XI
AVSS
AVSS
AVSS
AVDD
LF
VCOR
AVSS
VREF
REXT
CPS
AVSS
AVDD
TBIAS2 to 0
TB2N
TB2P
TA2N
TA2P
TB1N
TB1P
TA1N
I/O
I
I
—
—
I
I
—
O
—
I/O
I/O
—
I/O
I/O
—
I/O
I/O
—
—
—
—
—
—
—
—
—
—
I
—
—
—
O
I
—
—
—
—
O
I
—
I
I
I
—
—
O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Function
Connected to ground.
Connected to ground.
Ground.
Ground.
Link power status. Indicates whether link power is off or on. L: OFF H: ON
Link request. Link issues a PHY register read, write, or bus request through LREQ pin.
Power supply.
49.152 MHz link system clock.PHY-Link interface and cable interface synchronized with SCLK.
Ground.
PHY-Link interface control signals.
PHY-Link interface control signals.
Power supply.
PHY-Link interface data signals.
PHY-Link interface data signals.
Ground.
PHY-Link interface data signals.
PHY-Link interface data signals.
Power supply.
Ground.
Ground.
Ground.
Ground.
Ground.
Ground.
Power supply.
Power supply.
Ground.
Power-up reset external condensor pin.
Analog power supply.
Analog ground.
Analog power supply.
Crystal connection. Crystal oscillator connecting pins.
Crystal connection. Crystal oscillator connecting pins.
Analog ground.
Analog ground.
Analog ground.
Analog power supply.
External loop filter connection pin.
External loop filter connection pin.
Analog ground.
External base resistance connection pin.
External base resistance connection pin.
Cable power status detection pin.
Analog ground.
Analog power supply.
Cable bias output pins.
Arbitration / speed signal / data output; arbitration / strobe input. Reverse-phase I/O pins.
Arbitration / speed signal / data output; arbitration / strobe input. Reverse-phase I/O pins.
Arbitration / speed signal / data output; arbitration / strobe input. Standard-phase I/O pins.
Arbitration / strobe output; arbitration / speed signal / data input. Reverse-phase I/O pins.
Arbitration / speed signal / data output; arbitration / strobe input. Reverse-phase I/O pins.
(Connected to ground.)
Arbitration / speed signal / data output; arbitration / strobe input. Reverse-phase I/O pins.
(Connected to ground.)
Arbitration / speed signal / data output; arbitration / strobe input. Standard-phase I/O pins.(Not used)
Summary of Contents for CDP-LSA1
Page 22: ...22 Adjustment Location BD BOARD SIDE B TP FE TP TE TP VC TP XPCK TP RFAC IC103 30 16 15 1 ...
Page 30: ...CDP LSA1 30 30 6 7 SCHEMATIC DIAGRAM MAIN 1 3 SECTION See page 28 for Printed Wiring Board ...
Page 35: ...CDP LSA1 35 35 6 11 SCHEMATIC DIAGRAM PANEL SECTION See page 33 for Waveforms ...
Page 37: ...CDP LSA1 37 37 6 13 SCHEMATIC DIAGRAM POWER SECTION ...