46
Pin. No.
55
56
57
58
59
60
61
62
63 to 70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86 to 94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
Pin Name
VSS
XINT
XCS
XWR
XRD
ALE
XRDY
VDD
A0 to 7
VSS
INTL/XM16
VSS
D3
D2
D1
D0
VSS
CTL1
CTL0
LREQ
VDD
SYSCLK
VSS
XRESET
TS0 to 8
VDD
HCLKOUT
GNCLK
TS9
DQSY
C2PO
SBSO
EXCK
WFCK
SCOR
TS16
TS17
TS18
VSS
VDD
A10/TS32
A9/TS31
A8/TS30
A7/TS29
A6/TS28
A5/TS27
VSS
A4/TS26
A3/TS25
A2/TS24
A1/TS23
A0/TS22
XRAS/TS21
I/O
—
O
I
I
I
I
O
—
I
—
I
—
I/O
I/O
I/O
I/O
—
I/O
I/O
O
—
I
—
I
O
—
O
O
O
O
I
I
O
I
I
O
O
O
—
—
O
O
O
O
O
O
—
O
O
O
O
O
O
Function
Ground.
Interrupt signal transmitted to host. (Not used.)
Chip select signal from host
Write signal from host
Read signal from host
Address latch signal from host (enabled for M16); Fixed at "H" for Intel
Ready signal transmitted to host (L = Ready)
Power supply.
Address bit 0 (when Intel host interface is used)
Ground.
Type of host to which connection is to be established. (L = M16; H = Intel)
Ground.
PHY interface data bus bit 3.
PHY interface data bus bit 2.
PHY interface data bus bit 1.
PHY interface data bus bit 0.
Ground.
PHY interface control bus bit 1
PHY interface control bus bit 0
PHY interface request signal
Power supply.
PHY interface system clock (49.152 MHz)
Ground.
System reset
Test output. (Not used.)
Power supply.
Clock obtained by splitting SYSCLK (24.576 MHz) (Not used.)
Clock obtained by dividing NCLK in two (6.144 MHz) (Not used.)
Test output. (Not used.)
Ubit reception frame pulse (Not used.)
CD C2 error input.
CD SubCode data.
CD SubCode read clock.
SubCode frame signal.
CD SubCode frame lead signal.
“8-bit clock synchronized to 512 fsin (Output at address 30, bit 4 = 1) (Not used.)”
“L/R clock synchronized to 512 fsin(Output at address 30, bit 4 = 1) (Not used.)”
DRAM address bit 11. (Not used.)
Ground.
Power supply.
DRAM address bit 10. (Not used.)
DRAM address bit 9. (Not used.)
DRAM address bit 8. (Not used.)
DRAM address bit 7. (Not used.)
DRAM address bit 6. (Not used.)
DRAM address bit 5. (Not used.)
Ground.
DRAM address bit 4. (Not used.)
DRAM address bit 3. (Not used.)
DRAM address bit 2. (Not used.)
DRAM address bit 1. (Not used.)
DRAM address bit 0. (Not used.)
DRAM XRAS. (Not used.)
Summary of Contents for CDP-LSA1
Page 22: ...22 Adjustment Location BD BOARD SIDE B TP FE TP TE TP VC TP XPCK TP RFAC IC103 30 16 15 1 ...
Page 30: ...CDP LSA1 30 30 6 7 SCHEMATIC DIAGRAM MAIN 1 3 SECTION See page 28 for Printed Wiring Board ...
Page 35: ...CDP LSA1 35 35 6 11 SCHEMATIC DIAGRAM PANEL SECTION See page 33 for Waveforms ...
Page 37: ...CDP LSA1 37 37 6 13 SCHEMATIC DIAGRAM POWER SECTION ...
