Sony BRAVIA KDL-32V2000, Service Manual

Page: 53 / 100

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~ FEE Board Schematic Diagram [ Digital Microprocessor ] Page 1/6 ~
VDCLK,VDO[0-7]
FCSB0
XX
C3127
10p
C3130
XX
C3129
FWEB
CARD_RESET
100
R3111
TXD1B
100
R3104
0uH
FB3114
4.7k
R3106
FOEB
XX
C3115
VDO_VVSB
10p
C3131
+2V5D
SD
A_TV
100
R3109
RXD0B
CVBS
100
R3103
AT
X
JL3118
TXD3B
+3V3D
+3V3D
YUV_Y YUV_V
+3V3D
TXD0B VDO_VHSB
+1V5D
+3V3D
XX
C3128
10
C3140
VDO_FLD
RXD1B
nMASTER_RESET
100
R3112
XX
R3135
CD2B
16V
10
C3116
PWMOUT
CD1B
100
R3110
10p
C3132
YUV_U
RXD3B
+1V5D
CLK27M
XX
FB3100
SCL_TV
4.7k
R3105
100
R3101
100
R3102
JL3120
nCI_W
AIT
JL3116
JL3117
REGB
IO
WRB
IORDB
INP
A
CKB
VS1B
IREQB
IOIS16B
+3V3D
DQ[0-15]
D
A
DD[0-12]
DBA0,DBA1,DCASB
,DCKE,DCLK,DCLKB
,DCSB
,DQM0,DQM1,DQS0,DQS1,DRASB
,D
VREF
,D
WEB
JL3111
JL3110 JL3108 JL3106
NAND_ALE,NAND_CLE,NAND_RBB
JTCK,JTDI,JTDO
,JTMS
,JTRST
,NMI_EDINT
ABCK,ADO
,ALRCK,AMCK
JL3115
RADD[19-25]
XX
R3116
D3100
XX
JL3103 JL3104 JL3105 JL3107 JL3109 JL3112 JL3113 JL3114
IN_TSBCLK IN_TSPV
AL
nFE_RESET
FTV_CONFIG3 FTV_CONFIG0 FTV_CONFIG1 FTV_CONFIG2
JL3100
PMSINS
PMSSCLK PMSDIO PMSBS
JIG_MODE
YC_Y YC_C
0uH
FB3103
0uH
FB3104
0uH
FB3105
0uH
FB3106
0uH
FB3107
0uH
FB3108
0uH
FB3109
0uH
FB3110
0uH
FB3111
XX
FB3112
XX
FB3101
XX
FB3102
CE1B
RADD[0-14]
XX
R3107
XX
R3108
0uH
FB3113
10uH
L3100
XX
R3124
47
R3125
10k
R3113
10k
R3114
10k
R3115
+3V3D
0
R3126
JL3125
XX
R3139
JL3124
XX
R3141
XX
R3140
JL3123
JL3121
JL3122
0
R3138
0uH
FB3115
0uH
FB3116
SD
A_COFDM
SCL_COFDM
+1V5D
nW
AX2_TUNER
47
R3142
47
R3143
47
R3144
XX
R3145
200
R3129
200
R3127
200
R3128
200
R3130
200
R3132
200
R3131
R3149
0
470
R3136
XX
R3137
330
R3133
680
R3134
+3V3D
+5V_AUDIO_DAC
XX
R3152
10k
R3100
10k
R3150
10k
R3146
10k
R3151
10k
R3147
10k
R3148
E5
E17
F5
F17
G5
G17
T17
U5
U6
U17
E8
E9
E10
E11
E12
E13
E6
E7
E14
E15
E16
H5
H17
J5
J17
K5
K17
L5
L17
M5
N5
P5
P17
R5
T5
U7
U8
U9
U10
U14
U15
U16
R17 P21 R20 R21 T20 T21 U18 U19 U20 U21 AA3
Y4 W4 W3 V5 Y3
AA2 V15 AA1 W15 Y15 AA5 AA6
B5
C5 M19 L20 W19
AA19
N18 L21
Y8
AA8
Y7
AA7 P19 R18 N20 V18 P18 W18 T19 T18 N21 P20 R19
V9 W7 Y6 V8
W6
Y5
AA4 W5
V6
D20 F19 F18 E21 E19 H21 E20 M18 N19 E18 B17 C17 D17 D21 M20 K21 A17 C18 B21 A21 B20 A20 A19 B18 A18 G20 G19 G18 F21 D18 C21 C20 C19 K18 J21 J20 J19 H19 H18 G21 J18
F20
D19 B19
L19
L18 K20 K19 V21 V20 W21 W20 Y21 Y20
AA21
V19 Y19
V11
V12 W12 AA12
AA13
Y12
W13 Y11 Y13 W11 V14 W14 Y14 AA14
M17
J9
J10
J11
J12
J13
K9
K10
K11
K12
K13
L9
L10
L11
L12
L13
M9
M10
M11
M
12
M13
N9
N10
N11
N12
N13
U11
U12
U13
V13
W10
V10
AA10
Y9
W9
W8
AA9
A16 B16 A15 B15 A14 B14 A13 B13 D13 C13 D14 C14 D15 C15 D16 C16 D12
A9 B9 D8 A8 B8 A7 B7 A6 B6 D6 C6 D7 C7
C8
D9
A11 A12 C11 C12
C9 D10
C10 D11 B10 A10 B11 B12 Y17 W17 V17
AA17
AA16 Y16 W16 V16 AA15
A1 B2 A2 B3 A3 C4 B4 A4 A5 D5 F4 N4 P2 G2 R2 G1 K3 V1 C1 Y1 P3 B1 E4 F2 H1 R1 R3 T1 T3 U1 D1 D2 C3 U2 R4 V2 W2 V4 C2 D4 E2 J1 G3 J4 K4 L2 M2 N2 L4 M4 J3 H3 M1 N1 K1 N3 T2 M3 L3 H4 G4 J2 H2 F1 E3 E1 D3 V3 K2 L1 P1 T4
W1
U3 U4
AA18 Y18
Y2 P4 F3
AA11 Y10
V7
M21 N17
AA20
H20
UPD61123F1-100-KA3-A
IC3100
DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 D
A
DD13
D
A
DD12
D
A
DD11
D
A
DD10
DA
D
D
9
DA
D
D
8
DA
D
D
7
DA
D
D
6
DA
D
D
5
DA
D
D
4
DA
D
D
3
DA
D
D
2
DA
D
D
1
DA
D
D
0
DBA1 DBA0 UDQM UDQS LDQM LDQS DCSB DRASB DCASB DW
E
B
DCKE DCLK DCLKB DV
R
E
F
VDI_D7 / PPOR
T121
VDI_D6 / PPOR
T120
VDI_D5 / PPOR
T119
VDI_D4 / PPOR
T118
VDI_D3 / PPOR
T117
VDI_D2 / PPOR
T116
VDI_D1 / PPOR
T115
VDI_D0 / PPOR
T114
VDI_VCK / PPOR
T113
STP0_D
A
T7 / PPOR
T8
STP0_D
A
T6 / PPOR
T7
STP0_D
A
T5 / PPOR
T6
STP0_D
A
T4 / PPOR
T5
STP0_D
A
T3 / PPOR
T4
STP0_D
A
T2 / PPOR
T3
STP0_D
A
T1 / PPOR
T2
STP0_D
A
T0 / PPOR
T1
STP0_EN / PPOR
T9
STP0_CLK / PPOR
T0
REGB / PPOR
T34
IO
WRB / PPOR
T31
IORDB / PPOR
T30
INP
A
CKB / PPOR
T33
GPIO_VS1B / PPOR
T28
GPIO_RESET / PPOR
T32
GPIO_IREQB / PPOR
T24
GPIO_CD1B / PPOR
T26
GPIO_CD2B / PPOR
T35
PCE1B(CE2B_2) / PPOR
T36
PCE0B(CE2B_1) / PPOR
T27
IOSI16B / PPOR
T25
STP1_STR
T / PPOR
T38
STP1_EN / PPOR
T37
STP1_CLK / PPOR
T29
RD
A
T
A15 / STP1_D
A
T
7 / BOO
T_NAND_SEL1
RD
A
T
A14 / STP1_D
A
T
6 / BOO
T_NAND_SEL0
RD
A
T
A13 / STP1_D
A
T
5 / BOO
TSEL1
RD
A
T
A12 / STP1_D
A
T
4 / BOO
TSEL0
RD
A
T
A11 / STP1_D
A
T3 / MINIBOO
T
RD
A
T
A10 / STP1_D
A
T
2 / BWSEL
RD
A
T
A9 / STP1_D
A
T1 / R
OMBEND
RD
A
T
A8 / STP1_D
A
T0 / MCLKSEL2
RD
A
T
A7 / MCLKSEL1
RD
A
T
A6 / MCLKSEL0
RD
A
T
A5 /
VRCLKSEL1
RD
A
T
A4 /
VRCLKSEL0
RD
A
T
A3
RD
A
T
A2 / MRGMODE1
RD
A
T
A1 / MRGMODE0
RD
A
T
A0 / ENDIAN
RADD25 / HSD7 / EJT
A
G_MODE
RADD24 / HSD6 / DINT_EN RADD23 / HSD5 / DSYSELB RADD22 / HSD4 / PCI_MODE RADD21 / HSD3 / PCI_SIZE1 RADD20 / HSD2 / PCI_SIZE0 RADD19 / HSD1 / NAND_CS RADD18 / HSD0 RADD17 / PKTSTR
T
RADD16 / HSDE RADD15 / HSDCLK RADD14 RADD13 RADD12 RADD11 RADD10 RADD9 RADD8 RADD7 RADD6 RADD5 RADD4 RADD3 RADD2 RADD1 RADD0 FCSB1 FCSB0 FWEB FOEB NSEB NRBB NCLE NALE GCSB3 / PPOR
T50
GCSB2 / PPOR
T49
GCSB1 GCSB0 GRD
YB
RSTSWB RST
OUT
PWMOUT CLK27IN AV
D
D
P
AGNDP
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
AGNDV
AGNDV
AGNDV
AGNDV
TEST / GND
NMI/EDINT
JTRST
JTMS
JTDO
JTDI
JTCK
VDD3_USB
USBCLKI / PPOR
T105
USB_DP1 USB_DN1 USB_DP0 USB_DN0
USB_PPON1 / PPOR
T109
USB_OCI1 / PPOR
T
108
USB_PPON0 / PPOR
T107
USB_OCI0 / PPOR
T
106
MSD
A
T
A3 / PPOR
T127
MSD
A
T
A2 / PPOR
T126
MSD
A
T
A1 / PPOR
T132
MSDIO/D
A
T
A
0 / PPOR
T131
MSDIR / PPOR
T128
MSBS / PPOR
T130
MSCLK / PPOR
T129
TXD0B / CAP/COMP0 / PPOR
T110
RXD0B / CAP/COMP3 / PPOR
T137
CTS0B / CAP/COMP1 / PPOR
T111
R
T
S0B / CAP/COMP2 / PPOR
T112
TXD1B
RXD1B
R
T
S1B_B / STP0_STR
T
/ PPOR
T10
CTS1B_B / STP0_ERRB / PPOR
T11
DCD1B / PPOR
T55
RI1B / PPOR
T54
TXD2B / PPOR
T14
RXD2B / PPOR
T13
TXD3B / PPOR
T53
RXD3B / PPOR
T52
SD
A1
SCL1
SD
A0
SCL0
SCKINOUT / PPOR
T
46
SDIN / PPOR
T44
SDOUT / PPOR
T45
IR_IN_1 / PPOR
T47
IR_IN_0 / PPOR
T51
IR_OUT / PPOR
T48
SMRST0 / PPOR
T39
CMD
VCC0 / RI0B / PPOR
T40
OFF0 / DCD0B / PPOR
T41
SMCLK0 / DTR0B / PPOR
T42
SMD
A
T0 / DSR0B / PPOR
T43
A
O
1_D
A
T / PPOR
T125
A
O
1_LRCK / PPOR
T123
A
O
1_BCK / PPOR
T124
A
O
1_MCK / PPOR
T122
AO
0
_
D
A
T
A
O
0_LRCK
A
O
0_BCK
A
O
0_MCK
AT
X
P
A
R / PPOR
T56
FRAMEB / PPOR
T57
IRD
YB / PPOR
T58
TRD
YB / PPOR
T59
ST
OPB / PPOR
T60
IDSEL / PPOR
T61
DEVSELB / PPOR
T62
REQB0 / PPOR
T63
GNTB0 / PPOR
T64
PERRB / PPOR
T65
VDOE_VCK_IN / AD1 / PPOR
T70
VDOE_VVSB_IN / AD2 / PPOR
T71
VDOE_VHSB_IN / AD3 / PPOR
T72
VDOE_VCK / SERRB / PPOR
T66
VDOE_VVSB_OUT / INT
AB / PPOR
T67
VDOE_VHSB_OUT / PCICLK / PPOR
T68
VDOE_FLD / AD0 / PPOR
T69
VDOE_A7 / AD11 / PPOR
T80
VDOE_A6 / AD10 / PPOR
T79
VDOE_A5 / AD9 / PPOR
T78
VDOE_A4 / AD8 / PPOR
T77
VDOE_A3 / AD7 / PPOR
T76
VDOE_A2 / AD6 / PPOR
T75
VDOE_A1 / AD5 / PPOR
T74
VDOE_A0 / AD4 / PPOR
T73
VDOE_R7 / AD19 / PPOR
T88
VDOE_R6 / AD18 / PPOR
T87
VDOE_R5 / AD17 / PPOR
T86
VDOE_R4 / AD16 / PPOR
T85
VDOE_R3 / AD15 / PPOR
T84
VDOE_R2 / AD14 / PPOR
T83
VDOE_R1 / AD13 / PPOR
T82
VDOE_R0 / AD12 / PPOR
T81
VDOE_G7 / AD27 / PPOR
T96
VDOE_G6 / AD26 / PPOR
T95
VDOE_G5 / AD25 / PPOR
T94
VDOE_G4 / AD24 / PPOR
T93
VDOE_G3 / AD23 / PPOR
T92
VDOE_G2 / AD22 / PPOR
T91
VDOE_G1 / AD21 / PPOR
T90
VDOE_G0 / AD20 / PPOR
T89
VDOE_B7 / CBE3 / PPOR
T104
VDOE_B6 / CBE2 / PPOR
T103
VDOE_B5 / CBE1 / PPOR
T102
VDOE_B4 / CBE0 / PPOR
T101
VDOE_B3 / AD31 / PPOR
T100
VDOE_B2 / AD30 / PPOR
T99
VDOE_B1 / AD29 / PPOR
T98
VDOE_B0 / AD28 / PPOR
T97
VDO0_D7 / PPOR
T23
VDO0_D6 / PPOR
T22
VDO0_D5 / PPOR
T21
VDO0_D4 / PPOR
T20
VDO0_D3 / PPOR
T19
VDO0_D2 / PPOR
T18
VDO0_D1 / PPOR
T17
VDO0_D0 / PPOR
T16
VDO0_VCK / PPOR
T
15
VDO0_FLD / PPOR
T
12
VA
R
VA
G
VA
B
VA
Y
VA
C
V
A
CVBS VREF1 VREF0
RSET1 RSET0
AV
D
D
V
AV
D
D
V
AV
D
D
V
AV
D
D
V
VDD3
VDD3
VDD3
VDD3
VDD3
VDD3
VDD3
VDD3
VDD3
VDD3
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD1
VDD1
VDD1
VDD1
VDD1
VDD1
VDD1
VDD1
VDD1
VDD1
VDD1
VDD1
VDD1
VDD1
VDD1
VDD1
VDD1
VDD1
VDD1
VDD1
VDD1
VDD1
VDD1
VDD1
VDD1
VDD1
IN_TSD[0-7]
CTS0B RT
S
0
B
IN_TSPSYNC
nMODEM_OVR
MODEM_EN
nCI_OVR
nCI_EN
CI_PWR_EN
nSMC_INT
nSMC_RST
RD
A
T
A[0-15]
25V
4.7
C3100
25V
4.7
C3133
25V
4.7
C3136
10V
4.7
C3101
0.1
C3137
0.1
C3107
0.1
C3122
0.1
C3124
0.1
C3126
0.1
C3114
0.1
C3111
0.1
C3105
0.1
C3102
0.1
C3120
0.1
C3143
0.1
C3134
0.1
C3103
0.1
C3108
XX
C3119
0.1
C3141
XX
C3118
XX
C3117
0.1
C3138
0.1
C3123
0.1
C3110
0.1
C3104
0.1
C3113
0.1
C3112
0.1
C3139
0.1
C3135
0.1
C3106
0.1
C3125
0.1
C3121
0.1
C3109
0.1
C3142
0uH
FB3117
0uH
FB3118
+2V5D_DDR
B
U
F_MDO_STR
T
B
U
F_MDO_EN
B
U
F_MDO_CLK
10k
R3117
XX
R3118
R3119
0
nBO
ARD_RST
nBO
ARD_RST
NAND_WPB
0uH
FB3119
0uH
FB3120
0uH
FB3121
0uH
FB3122
0uH
FB3123
XX
FB3124
0uH
FB3125
B
U
F_MDO_CLK
B
U
F_MDO_EN
B
U
F_MDO_STR
T
DQ[0] DQ[1] DQ[2] DQ[3] DQ[4] DQ[5] DQ[6] DQ[7] DQ[8] DQ[9] DQ[10] DQ[11] DQ[12] DQ[13] DQ[14] DQ[15]
D
A
DD[0]
D
A
DD[1]
D
A
DD[2]
D
A
DD[3]
D
A
DD[4]
D
A
DD[5]
D
A
DD[6]
D
A
DD[7]
D
A
DD[8]
D
A
DD[9]
D
A
DD[10]
D
A
DD[11]
D
A
DD[12]
DRASB DCSB DQS0 DQM0 DQS1 DQM1 DBA0 DBA1 DCKE DW
E
B
DCASB DCLKB DCLK
RADD[22] RADD[23] RADD[24] RADD[25] RADD[20] RADD[21] RADD[19]
NAND_ALE NAND_CLE NAND_RBB NAND_SEB
JTRST
JTMS
JTDO
JTDI
JTCK
NMI_EDINT
ALRCK
ABCK
ADO
RADD[0] RADD[1] RADD[2] RADD[3] RADD[4] RADD[5] RADD[6] RADD[7] RADD[8] RADD[9] RADD[10] RADD[11] RADD[12] RADD[13] RADD[14]
GPIO[0]
GPIO[1] GPIO[2] GPIO[3] GPIO[4]
GPIO[5] GPIO[6]
GPIO[7]
D
A
DD[13]
VDO_FLD VDO[7] VDO[6] VDO[5] VDO[4] VDO[3] VDO[2] VDO[1] VDO[0]
VDCLK
DV
R
E
F
AMCK
CTS0B
RD
A
T
A[7]
RD
A
T
A[6]
RD
A
T
A[5]
RD
A
T
A[4]
RD
A
T
A[3]
RD
A
T
A[2]
RD
A
T
A[1]
RD
A
T
A[0]
RD
A
T
A[15]
RD
A
T
A[14]
RD
A
T
A[13]
RD
A
T
A[12]
RD
A
T
A[11]
RD
A
T
A[10]
RD
A
T
A[8]
RD
A
T
A[9]
IN_TSD[0] IN_TSD[1] IN_TSD[2] IN_TSD[3] IN_TSD[4] IN_TSD[5] IN_TSD[6] IN_TSD[7]
THESE CAP
A
C
IT
ORS
T
O
BE PLA
CED
UNDERNEA
TH BGA
THIS CAP
A
C
IT
OR
T
O
BE
PLA
CED UNDERNEA
TH BGA
THESE CAP
A
C
IT
ORS
T
O
BE PLA
CED UNDERNEA
TH BGA
THESE CAP
A
C
IT
ORS
T
O
BE PLA
CED UNDERNEA
TH BGA
THESE CAP
A
C
IT
ORS
T
O
BE PLA
CED UNDERNEA
TH BGA
DIFFERENTIAL P
A
IR
OF CLOCK SIGNALS
THIS CAP
A
C
IT
OR
T
O
BE
PLA
CED UNDERNEA
TH BGA
THIS CAP
A
C
IT
OR
T
O
BE
PLA
CED UNDERNEA
TH BGA
THIS CAP
A
C
IT
OR
T
O
BE
PLA
CED UNDERNEA
TH BGA
VDO_VHSB / VDO_VVSB /
Y U V
NOTE SYMBOL
IS WRONG
/ CTS1B / R
TS1B
BOARD VERSION RESISTORS - MOUNT ON
SIDE-A WITH JL’S ON SIDE-B
NOTE RESISTORS R3130..R3137 ARE 0.5% TOLERANCE
FEE
FEE-WAX2
1/6 DIGITAL MICROPROCESSOR
16V
COMPONENTS MARKED AS XX ARE NOT FITTED ON THIS MODEL