Sony BKP-7934, Installation And Maintenance Manual

Page: 30 / 64

4-8
BKP-7934 IMM
IC
SN74HC00APW-E05
SN74HC00APW-E20 (TI)
SN74HC04APW-E05
SN74HC04APW-E20 (TI)
SN74HC10APW-E05 (TI)
SN74HC125APW-E05 (TI)
SN74HC14APW-E05
SN74HC14APW-E20 (TI)
S-24S45IF10 (SEIKO I&E)
CE
IN
SK
IN
DI
IN
DO
OUT
INPUT
CE
SK
DI
RECALL
STORE
: CHIP ENABLE
: SERIAL CLOCK
: SERIAL DATA
: RECALL
: STORE
1
2
3
4
8
7
6
5
V
DD
GND
STORE
RECALL
C-MOS 256-BIT SERIAL NVRAM
—TOP VIEW—
1
2
3
6
7
CE
SK
DI
RECALL
STORE
DO
4
OUTPUT
DO : SERIAL DATA
CONTROL
LOGIC
ROW
DECODER
INSTRUCTION
REGISTER
CE
1
INSTRUCTION
DECODER
COLUMN
DECODER
4-BIT
COUNTER
DI
3
SK
2
RECALL
6
STORE
7
STATIC
RAM
256-BIT
V
DD
8
GND
5
DO
4
SN74HC08APW-E05 (TI)
1 2 3 4 5 6 7
14 13 12 11 10 9 8
GND
V
DD
A
0
0
1
1
B
0
1
0
1
Y
0
0
0
1
0
1
: LOW LEVEL
: HIGH LEVEL
A
B
A
B
Y Y =
Y = A • B =
A
+
B
C-MOS QUAD 2-INPUT AND GATES
—TOP VIEW—
14
V
DD
GND
13 12 11 10 9 8
1 2 3 4 5 6 7
A
0
0
0
0
1
1
1
1
0
1 : LOW LEVEL
: HIGH LEVEL
A
B
C A
B
C
Y = Y
Y =
ABC
=
A
+
B
+
C
B
0
0
1
1
0
0
1
1
C
0
1
0
1
0
1
0
1
Y
1
1
1
1
1
1
1
0
C-MOS 3-INPUT NAND GATE
—TOP VIEW—
A
B
A
B
Y = Y
14 13
V
DD
GND
12 11 10 9 8
7 6 5 4 3 2 1
A
0
0
1
1
B
0
1
0
1
Y
1
1
1
0
0 ; LOW LEVEL
1 ; HIGH LEVEL
Y = A • B = A + B
C-MOS QUAD 2-INPUT NAND GATES
—TOP VIEW—
G A Y
0 0
HI-Z
1
0
1
x
HI-Z
: LOW LEVEL
: HIGH LEVEL
: DON’T CARE
: HIGH IMPEDANCE
V
DD
GND
10 9 8
7 6 5 1 2 3 4
11 12 14 13
x 1
1 0
0
Y A
G
C-MOS BUS BUFFER GATES WITH 3-STATE OUTPUT
—TOP VIEW—
A A Y = Y
14 13
V
DD
GND
12 11 10 9 8
7 6 5 4 3 2 1
A
0
1
Y
1
0
0 : LOW LEVEL
1 : HIGH LEVEL
Y =
A
C-MOS HEX INVERTERS
—TOP VIEW—
GND
V
DD
1 2 3 4 5 6 7
8
0
1 : LOW LEVEL
: HIGH LEVEL
A
Y
A
0
1
Y = A
Y = A
14 13 12 11 10 9
Y
1
0
C-MOS HEX SCHMITT TRIGGER INVERTERS
—TOP VIEW—