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USB 2.0 High-Speed 3-Port Hub Controller

Datasheet

SMSC USB2513

Revision 1.98 (11-19-07)

DATASHEET

4.7.2.2

RESET_N for EEPROM Configuration

Figure 4.5 Reset_N Timing for EEPROM Mode

Notes:

When in Bus-Powered mode, the Hub and its associated circuitry must not consume more than
100mA from the upstream USB power source during t4+t5+t6+t7.

All Power Supplies must have reached the operating levels mandated in

Chapter 5, DC

Parameters

, prior to (or coincident with) the assertion of RESET_N.

Table 4.6 Reset_N Timing for EEPROM Mode

NAME

DESCRIPTION

MIN

TYP

MAX

UNITS

RESET_N Asserted.

sec

Hub Recovery/Stabilization.

500

sec

EEPROM Read / Hub Config.

2.0

99.5

msec

USB Attach (See Note).

100

msec

Host acknowledges attach and signals USB
Reset.

100

msec

USB Idle.

undefined

msec

Completion time for requests (with or without data
stage).

msec

RESET_N

VSS

Hardware

reset

asserted

Read Strap

Options

Read EEPROM

Set Options

Attach

USB

Upstream

USB Reset

recovery

Idle

Start

completion

request

response

Summary of Contents for USB2513

Page 1: ...ble Features Customize Vendor ID Product ID and Device ID Select whether the hub is part of a compound device When any downstream port is permanently hardwired to a USB peripheral device the hub is pa...

Page 2: ...s or errors known as anomalies which may cause the product s functions to deviate from published specifications Anomaly sheets are available upon request SMSC products are not designed intended author...

Page 3: ...ROM Programming 33 4 4 SMBus Slave Interface 34 4 4 1 Bus Protocols 34 4 4 2 Invalid Protocol Response Behavior 35 4 4 3 General Call Address Response 35 4 4 4 Slave Device Time Out 35 4 4 5 Stretchin...

Page 4: ...igure 4 1 Block Write 34 Figure 4 2 Block Read 35 Figure 4 3 LED Strapping Option 37 Figure 4 4 Reset_N Timing for Default Strap Option Mode 38 Figure 4 5 Reset_N Timing for EEPROM Mode 39 Figure 4 6...

Page 5: ...514 Buffer Type Descriptions 16 Table 4 1 36 QFN and 48 QFN Feature Differences 18 Table 4 2 Internal Default EEPROM and SMBus Register Memory Map 19 Table 4 3 Port Remap Register for Ports 1 2 31 Tab...

Page 6: ...RESET_N 24 HS_IND CFG_SEL1 23 SCL SMBCLK CFG_SEL0 22 SDA SMBDATA NON_REM1 21 NC 20 NC 19 VBUS_DET 27 OCS3_N 18 PRTPWR3 17 OCS2_N 16 PRTPWR2 15 OCS1_N 14 VDD33CR 13 VDD18 12 PRTPWR1 11 TEST 10 VDDA33...

Page 7: ...KIN 45 RBIAS 48 VDD33PLL 47 VDD18PLL 46 USBUP_DM 42 VDDA33 1 USBDN1_DM PRT_DIS_M1 2 USBDN1_DP PRT_DIS_P1 3 USBDN2_DM PRT_DIS_M2 4 USBDN2_DP PRT_DIS_P2 5 USBDN3_DM PRT_DIS_M3 6 USBDN3_DP PRT_DIS_P3 7 N...

Page 8: ...ce PLL 24 MHz Crystal To EEPROM or SMBus Master Routing Port Re Ordering Logic SCK SD TT 3 Port Controller PHY 1 Port 1 OC Sense Switch Driver LED Drivers USB Data Downstream OC Sense Switch LED Drive...

Page 9: ...ata signals Host port or upstream hub VBUS_DET 27 35 I O12 Detect Upstream VBUS Power Detects state of Upstream VBUS power The SMSC Hub monitors VBUS_DET to determine when to assert the internal D pul...

Page 10: ...M is swapped and the LED is active low LED_B3_N GANG_EN n a 22 I O12 Enhanced Port 3 LED Gang Power and Overcurrent Strap Option Enhanced Indicator LED for port 3 Will be active low when LED support i...

Page 11: ...ity of the 3 1 PRTPWR pins While RESET_N is asserted the logic state of this pin will through the use of internal combinatorial logic determine the active state of the 3 1 PRTPWR pins in order to ensu...

Page 12: ...3 are non removable SCL SMBCLK CFG_SEL0 24 31 I OSD12 Serial Clock SCL SMBus Clock SMBCLK Configuration Select_SEL0 The logic state of this multifunction pin is internally latched on the rising edge o...

Page 13: ...f the crystal or to an external 24 48MHz clock when a crystal is not used Note 48MHz only available in 48 QFN XTAL2 32 44 OCLKx Crystal Output 24MHz Crystal This is the other terminal of the crystal o...

Page 14: ...ports are removable and the LED is active high NON_REM 1 0 01 Port 1 is nonremovable and the LED is active low NON_REM 1 0 10 Ports 1 2 are non removable and the LED is active high NON_REM 1 0 11 Port...

Page 15: ...in QFN 0 0 1 36 Pin QFN N A 1 0 Internal Default Configuration Strap Options Enabled Bus Power Operation LED Mode USB 48 Pin QFN 0 1 0 36 Pin QFN N A 1 1 2 Wire I2C EEPROMS are supported Strap Options...

Page 16: ...Filtered analog power for internal PLL If the internal regulator is enabled then this pin must have a 1 0 F or greater 20 ESR 0 1 capacitor to VSS VDDA33 5 10 29 5 10 41 VDD Analog I O 3 3V Filtered a...

Page 17: ...pen drain 12mA sink with Schmitt trigger and must meet I2C Bus Specification Version 2 1 requirements ICLKx XTAL clock input OCLKx XTAL clock output I R RBIAS I O U Analog Input Output Defined in USB...

Page 18: ...mmediately after RESET_N negation 4 1 1 1 Power Switching Polarity The selection of active state polarity for the PRTPWR pins is made by a strapping option only the PRTPWR_POL pin Note If PRTPWR_POL i...

Page 19: ...vailable 4 3 1 Internal Register Set Common to EEPROM and SMBus Table 4 2 Internal Default EEPROM and SMBus Register Memory Map REG ADDR R W REGISTER NAME ABBR INTERNAL DEFAULT ROM SMBUS AND EEPROM PO...

Page 20: ...R W Reserved N A 00h 0x00 FFh R W Status Command Note SMBus register only STCD 00h 0x00 BIT NUMBER BIT NAME DESCRIPTION 7 0 VID_LSB Least Significant Byte of the Vendor ID This is a 16 bit value that...

Page 21: ...BIT NAME DESCRIPTION 7 0 PID_MSB Most Significant Byte of the Product ID This is a 16 bit value that the Vendor can assign that uniquely identifies this particular product assigned by OEM This field i...

Page 22: ...ng is enabled this bit is ignored and the LOCAL_PWR pin is used to determine if the hub is operating from self or bus power 6 Reserved Reserved 5 HS_DISABLE High Speed Disable Disables the capability...

Page 23: ...Dynamic Power switching is enabled the Hub detects the availability of a local power source by monitoring the external LOCAL_PWR pin If the Hub detects a change in power source availability the Hub im...

Page 24: ...kage being used in the implementation Note The Hub will only report that it supports LED s to the host when USB mode is selected All other modes will be reported as No LED Support 0 STRING_EN Enables...

Page 25: ...7 Reserved Bit 6 Reserved Bit 5 Reserved Bit 4 Reserved Bit 3 1 Port 3 is disabled Bit 2 1 Port 2 is disabled Bit 1 1 Port 1 is disabled Bit 0 is Reserved always 0 BIT NUMBER BIT NAME DESCRIPTION 7 0...

Page 26: ...NAME DESCRIPTION 7 0 MAX_PWR_BP Max Power Bus_Powered Value in 2mA increments that the Hub consumes from an upstream port VBUS when operating as a bus powered hub This value includes the hub silicon a...

Page 27: ...d power consumption from VBUS of all associated circuitry on the board This value will NOT include the power consumption of a permanently attached peripheral if the hub is configured as a compound dev...

Page 28: ...h the LSB at the least significant address and the MSB at the next 8 bit location subsequent characters must be stored in sequential contiguous address in the same LSB MSB manner Some EEPROM programme...

Page 29: ...for Upstream Port 00 Normal electrical drive strength No boost 01 Elevated electrical drive strength Low approximately 4 boost 10 Elevated electrical drive strength Medium approximately 8 boost 11 Ele...

Page 30: ...ength No boost 01 Elevated electrical drive strength Low approximately 4 boost 10 Elevated electrical drive strength Medium approximately 8 boost 11 Elevated electrical drive strength High approximate...

Page 31: ...see PRTMAP_EN in Register 08h Configuration Data Byte 3 the hub s downstream port numbers can be remapped to different logical port numbers assigned by the host Note The OEM must ensure that Contiguou...

Page 32: ...b is the Physical Port Number When remapping mode is enabled see PRTMAP_EN in Register 08h Configuration Data Byte 3 the hub s downstream port numbers can be remapped to different logical port numbers...

Page 33: ...rotocol 4 3 2 2 Pull Up Resistor The Circuit board designer is required to place external pull up resistors 10K recommended on the SDA SMBDATA SCL SMBCLK CFG_SELO lines per SMBus 1 0 Specification and...

Page 34: ...egister set is shown in Section 4 3 1 Internal Register Set Common to EEPROM and SMBus on page 19 4 4 1 Bus Protocols Typical Write Block and Read Block protocols are shown below Register accesses are...

Page 35: ...e to undefined registers 4 4 3 General Call Address Response The Hub does not respond to a general call address of 0000_000b 4 4 4 Slave Device Time Out According to the SMBus Specification V1 0 devic...

Page 36: ...at are loaded when this option is selected 4 6 Default Strapping Options The USB2514 can be configured via a combination of internal default values and pin strap options Please see Table 3 1 and Table...

Page 37: ...ub and its associated external circuitry consumes less than 500 A of current from the upstream USB power source Assertion of RESET_N external pin causes the following 1 All downstream ports are disabl...

Page 38: ...T_N Table 4 5 Reset_N Timing for Default Strap Option Mode NAME DESCRIPTION MIN TYP MAX UNITS t1 RESET_N Asserted 1 sec t2 Strap Setup Time 16 7 nsec t3 Strap Hold Time 16 7 1400 nsec t4 hub outputs d...

Page 39: ...er 5 DC Parameters prior to or coincident with the assertion of RESET_N Table 4 6 Reset_N Timing for EEPROM Mode NAME DESCRIPTION MIN TYP MAX UNITS t1 RESET_N Asserted 1 sec t2 Hub Recovery Stabilizat...

Page 40: ...B Bus Reset In response to the upstream port signaling a reset to the Hub the Hub does the following Note The Hub does not propagate the upstream USB reset to downstream devices 1 Sets default address...

Page 41: ...7 DATASHEET 5 Moves device from suspended to active if suspended 6 Complies with Section 11 10 of the USB 2 0 Specification for behavior after completion of the reset sequence The Host then configures...

Page 42: ...when the AC power is switched on or off In addition voltage transients on the AC power line may appear on the DC output When this possibility exists it is suggested that a clamp circuit be used 5 2 Re...

Page 43: ...el Low Input Leakage High Input Leakage VILI VIHI IILL IIHL 2 0 35 10 0 8 90 10 V V uA uA TTL Levels VIN 0 VIN VDD33 Input Buffer with Pull Down IPD Low Input Level High Input Level Low Input Leakage...

Page 44: ...0 mA mA Supply Current Configured High Speed Host 1 Port HS 1 Port LS FS 2 Ports LS FS 2 Ports HS 3 Ports HS IHCH1C1 IHCC2 IHCH2 IHCH3 150 140 155 160 160 150 250 260 mA mA mA mA All supplies combined...

Page 45: ...TASHEET CAPACITANCE TA 25 C fc 1MHz VDD18 VDDPLL 1 8V Table 5 2 Pin Capacitance LIMITS PARAMETER SYMBOL MIN TYP MAX UNIT TEST CONDITION Clock Input Capacitance CXTAL 2 pF All pins except USB pins and...

Page 46: ...6 1 1 SMBus Interface The SMSC Hub conforms to all voltage power and timing characteristics and specifications as set forth in the SMBus 1 0 Specification for Slave Only devices except as noted in Sec...

Page 47: ...SMSC USB2513 47 Revision 1 98 11 19 07 DATASHEET USB 2 0 High Speed 3 Port Hub Controller Datasheet Chapter 7 Package Outlines Figure 7 1 36 Pin QFN 6x6mm Body 0 5mm Pitch...

Page 48: ...SMSC USB2513 48 Revision 1 98 11 19 07 DATASHEET USB 2 0 High Speed 3 Port Hub Controller Datasheet Figure 7 2 48 Pin QFN 7x7mm Body 0 5mm Pitch...

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