Silicon Systems SiliconDrive SSD-P16G(I)-3100 Datasheet Download Page 68

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ATA R

EGISTERS

SSD-P

XXX

(I)-3100 D

ATA

HEET

ILICON

YSTEMS

ROPRIETARY

This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc.

All unauthorized use and/or reproduction is prohibited.

3100P-06DSR

AGE

EBRUARY

2, 2009

EVICE

DDRESS

EGISTER

The Device Address register is used to maintain compatibility with ATA disk
drive interfaces.

Table 45: Device Address Register

Operation

Read/Write

nWTG nHS3 nHS2 nHS1 nHS0 nDS1 nDS0

Default Value

Bit(s)

Description

Reserved bit.

Write Gate (nWTG).

Low when a write to the device is in process.

5-2

nHS3 to nHS0.

The negated binary address of the currently selected

head.

nDS1.

Low when drive 1 is selected and active.

nDS0.

Low when drive 0 is selected and active.

Summary of Contents for SiliconDrive SSD-P16G(I)-3100

Page 1: ...integrated with SiliconSystems patented PowerArmor and patent pending SiSMART technologies to virtually eliminate storage systems failures PowerArmor prevents data corruption and loss from power disturbances by integrating patented technology into every SiliconDrive SiSMART acts as an early warning system to eliminate unscheduled downtime by constantly monitoring and reporting the exact amount of ...

Page 2: ...Operational Life Span 3100P 05DSR May 13 2008 Updated Overview SiProtect information SSDS04 3100P R January 28 2008 Added a Note below the DC Characteristics table SSDS03 3100P R December 11 2007 Updated the tRWD Maximum in the True IDE Multiword DMA Read Write Access Timing table SSDS02 3100P R July 25 2007 Updated Cylinder Low in the Task File Register Specification table Sample Label Removed NO...

Page 3: ...ns 1 Physical Dimensions 1 Product Specifications 2 System Performance 2 System Power Requirements 2 Reliability 3 Projected Operational Life Span 3 Product Capacity Specifications 4 Environmental Specifications 4 Electrical Specification 5 Pin Assignments 5 Signal Descriptions 7 Absolute Maximum Ratings 15 Capacitance 16 DC Characteristics 16 AC Characteristics 17 Attribute and Common Memory Read...

Page 4: ...d Status Register 202h 38 Pin Placement Register 204h 39 Socket and Copy Register 206h 40 Common Memory Description and Operation 41 Common Memory Read Operations 41 Common Memory Write Operations 41 I O Space Description and Operation 42 I O Space Read Operations 42 I O Space Write Operations 42 ATA and True IDE Register Decoding 43 Memory Mapped Register Decoding 43 Independent I O Mode Register...

Page 5: ...8 ATA Command Block and Set Description 59 ATA Command Set 59 Check Power Mode 98h E5h 61 Executive Drive Diagnostic 90h 62 Format Track 50h 63 Identify Drive ECh 64 Identify Drive Drive Attribute Data 65 Idle 97h E3h 68 Idle Immediate 95h E1h 69 Initialize Drive Parameters 91h 70 Recalibrate 1Xh 71 Read Buffer E4h 72 Read DMA C8h 73 Read Multiple C4h 74 Read Sector 20h 21h 75 Read Long Sector s 2...

Page 6: ... prohibited 3100P 06DSR PAGE VI FEBRUARY 2 2009 Write DMA CAh 85 Write Multiple C5h 86 Write Sector s 30h 31h 87 Write Long Sector s 32h 33h 88 Erase Sector s C0h 89 Request Sense 03h 90 Translate Sector 87h 91 Wear Level F5h 92 Write Multiple w o Erase CDh 93 Write Sector s w o Erase 38h 94 Write Verify 3Ch 95 Sales and Support 96 Part Numbering 96 Nomenclature 96 Part Numbers 97 Sample Label 97 ...

Page 7: ...d 3100P 06DSR PAGE VII FEBRUARY 2 2009 LIST OF FIGURES Figure 1 Physical Dimensions 1 Figure 2 Attribute and Common Memory Read Timing Diagram 17 Figure 3 Attribute and Common Memory Write Timing Diagram 18 Figure 4 I O Access Read Timing Diagram 19 Figure 5 I O Access Write Timing Diagram 20 Figure 6 True IDE Read Write Access Timing Diagram 21 Figure 7 True IDE Multiword DMA Read Write Access Ti...

Page 8: ...ngs 15 Table 10 Capacitance 16 Table 11 DC Characteristics 16 Table 12 Attribute and Common Memory Read Timing 17 Table 13 Attribute and Common Memory Write Timing 18 Table 14 I O Access Read Timing 19 Table 15 I O Access Write Timing 20 Table 16 True IDE Read Write Access Timing 21 Table 17 True IDE Multiword DMA Read Write Access Timing 22 Table 18 Attribute Memory Read Operations 23 Table 19 At...

Page 9: ...ter 47 Table 35 Feature Register 48 Table 36 Sector Count Register 49 Table 37 Sector Number Register 50 Table 38 Cylinder Low Register 51 Table 39 Cylinder High Register 52 Table 40 Drive Head Register 53 Table 41 Status Register 54 Table 42 Command Register 55 Table 43 Alternate Status Register 56 Table 44 Device Control Register 57 Table 45 Device Address Register 58 Table 46 ATA Command Block ...

Page 10: ...s EFh 79 Table 65 Set Features Attributes 79 Table 66 Set Multiple Mode C6h 80 Table 67 Set Sleep Mode 99h E6h 81 Table 68 Standby 96h E2h 82 Table 69 Standby Immediate 94h E0h 83 Table 70 Write Buffer E8h 84 Table 71 Write DMA CAh 85 Table 72 Write Multiple C5h 86 Table 73 Write Sector s 30h 31h 87 Table 74 Write Long Sector s 32h 33h 88 Table 75 Erase Sector s C0h 89 Table 76 Request Sense 03h 9...

Page 11: ...ll unauthorized use and or reproduction is prohibited 3100P 06DSR PAGE 1 FEBRUARY 2 2009 PHYSICAL SPECIFICATIONS The SiliconDrive PC Card products are offered in a Type II form factor See Part Numbering on page 96 for details regarding PC Card capacities PHYSICAL DIMENSIONS This section provides diagrams that describe the physical dimensions for the PC Card Figure 1 Physical Dimensions ...

Page 12: ...typical at 25 C and nominal supply voltage SYSTEM PERFORMANCE SYSTEM POWER REQUIREMENTS Note The 5V is the only operation for the 16GB capacity Table 1 System Performance Reset to Ready Startup Time Typical Maximum 200ms 400ms Read Transfer Rate Typical 8MBps Write Transfer Rate Typical 6MBps Burst Transfer Rate 16 7MBps Controller Overhead Command to DRQ 2ms maximum Table 2 System Power Requireme...

Page 13: ...ve is dependant on the customer usage model SiSMART is a patented technology of SiliconSystems that enables host systems to monitor actual usage of a SiliconDrive in real time SiSMART measures and reports the remaining life of a SiliconDrive For more information on SiSMART refer to the Eliminating Unscheduled Downtime by Forecasting Useable Life white paper at http www siliconsystems com technolog...

Page 14: ...s Number of Heads Numberof Sectors Track 32MB 32 702 464 63 872 499 4 32 64MB 65 601 536 128 128 1001 4 32 128MB 130 154 496 254 208 993 8 32 256MB 260 571 136 508 928 994 16 32 512MB 521 773 056 1 019 088 1011 16 63 1GB 1 047 674 880 2 046 240 2030 16 63 2GB 2 098 446 336 4 098 528 4066 16 63 4GB 4 224 761 856 8 251 488 8186 16 63 8GB 8 455 200 768 16 514 064 16 383 16 63 16GB 16 494 428 160 32 2...

Page 15: ...5 GND GND GND 2 D3 D3 D3 36 CD1 CD1 CD1 3 D4 D4 D4 37 D111 D111 D111 4 D5 D5 D5 38 D121 D121 D121 5 D6 D6 D6 39 D131 D131 D131 6 D7 D7 D7 40 D141 D141 D141 7 CE1 CE1 CS0 41 D151 D151 D151 8 A10 A10 A102 42 CE2 CE2 CS1 9 OE OE OE 2 43 VS1 VS1 VS1 10 NU NU NU 44 IORD IORD IORD 11 A9 A9 A92 45 IOWR IOWR IOWR 12 A8 A8 A82 46 NU NU NU 13 NU NU NU 47 NU NU NU 14 NU NU NU 48 NU NU NU 15 WE WE WE 3 49 NU ...

Page 16: ...9 Notes 28 A1 A1 A1 62 BVD23 SPKR 3 DASP 29 A0 A0 A0 63 BVD1 STSCHG PDIAG 30 D0 D0 D0 64 D81 D81 D81 31 D1 D1 D1 65 D91 D91 D91 32 D2 D2 D2 66 D101 D101 D101 33 WP IOIS16 IOCS16 67 CD2 CD2 CD2 34 GND GND GND 68 GND GND GND NU Not used 1 These signals are required only for 16 bit access and not required when installed in 8 bit systems 2 Should be grounded by the host Pin PC Card Memory Mode PC Card...

Page 17: ... its configuration control and status registers A10 A0 PC Card I O mode This signal is the same as the PC Card Memory Mode signal A2 A0 True IDE mode 18 19 20 I In true IDE mode only A 2 0 are used to select the one of eight registers in the Task File The remaining address lines should be grounded by the host BVD1 PC Card memory mode 46 I O This signal is asserted high because BVD1 is not supporte...

Page 18: ...ive CF and are used by the host to determine that the SiliconDrive CF is fully inserted into its socket CD1 CD2 PC Card I O Mode This signal is the same for all modes CD1 CD2 True IDE mode This signal is the same for all modes CE1 CE2 PC Card memory mode Card Enable 7 32 I These input signals are used both to select the card and to indicate to the card whether a byte or a word operation is being p...

Page 19: ...ster CSEL PC Card memory mode 39 I This signal is not used for this mode CSEL PC Card I O mode This signal is not used for this mode CSEL True IDE mode This internally pulled up signal is used to configure this device as a master or slave when configured in the true IDE mode When this pin is Grounded this device is configured as a master Open this device is configured as a slave INPACK PC Card mem...

Page 20: ...ing DMARQ and reasserts DMARQ if there is more data to transfer The DMARQ DMACK handshake is used to provide flow control during the transfer D15 D00 PC Card memory mode 31 30 29 28 27 49 48 47 6 5 4 3 2 23 22 21 I O These lines carry the data commands and status information between the host and the controller D00 is the LSB of the word s even byte D08 is the LSB of the word s odd byte D15 D00 PC ...

Page 21: ...mode IOWR PC Card memory mode 35 I This signal is not used in this mode IOWR PC Card I O mode The I O write strobe pulse is used to clock I O data on the Card data bus into the SiliconDrive CF controller registers when the SiliconDrive CF is configured to use the I O interface The clocking occurs on the negative to positive edge of the signal the trailing edge IOWR True IDE mode In true IDE mode t...

Page 22: ...resistor At power up and reset the RDY BSY signal is held low busy until the SiliconDrive CF has completed its power up or reset function No access of any type should be made to the SiliconDrive CF during this time The RDY BSY signal is held high disabled from being busy whenever the SiliconDrive CF has been powered up with RESET continuously disconnected or asserted IREQ PC Card I O mode Input Ac...

Page 23: ...In true IDE mode this signal is used by the host in response to DMARQ to initiate DMA transfers The DMARQ DMACK handshake is used to provide flow control during the transfer When DMACK is asserted CS0 and CS1 are not asserted and transfers are 16 bits wide RESET PC Card memory mode 41 I When the pin is high this signal resets the SiliconDrive CF The SiliconDrive CF is reset only at power up if thi...

Page 24: ... VS2 True IDE mode This signal is the same for all modes WAIT PC Card memory mode 42 O The WAIT signal is driven low by the SiliconDrive CF to signal the host to delay completion of a memory or I O cycle that is in progress WAIT PC Card I O mode This signal is the same as the PC Card Memory Mode signal IORDY True IDE mode In true IDE mode this output signal may be used as IORDY WE PC Card memory m...

Page 25: ... completion of the reset initialization sequence IOIS16 PC Card I O mode I O Operation When the SiliconDrive CF is configured for I O operation pin 24 is used for the I O Selected which is a 16 bit port IOIS16 function A low signal indicates that a 16 bit or odd byte only operation can be performed at the addressed port IOIS16 True IDE mode In true IDE mode this output signal is asserted low when ...

Page 26: ...Units Cin Input Capacitance 35 pF Cout Output Capacitance 35 pF CI O Bidirectional Capacitance 35 pF Table 11 DC Characteristics Symbol Parameter 3 3 V 10 5V 10 Units Minimum Maximum Minimum Maximum VCC Power Supply Voltage 3 0 3 6 4 5 5 5 V ILI Input Leakage 1 Current 5 5 μA ILO Output Leakage 1 Current 5 5 μA VCCR VCC Read Current 50 80 mA VCCW VCC Write Current 50 80 mA VCCS VCC Standby Current...

Page 27: ...able 12 Attribute and Common Memory Read Timing Symbol Parameter Minimum Maximum Units tRC Read Cycle Time 100 ns tA A Address Access Time 100 ns tA CE Card Enable Access Time 100 ns tA OE Output Enable Access Time 50 ns tDIS OE Output Disable Time from OE 50 ns tEN OE Output Enable Time from OE 5 ns tAXQX Data Valid from Address Change 0 ns tAVWL Address Setup Time 10 ns tAXQX Address Hold Time 1...

Page 28: ...LWH Write Pulse Width 60 ns tAVWL Address Setup Time 10 ns tAVWH Address Setup Time for WE 70 ns tELWH Card Enable Setup Time for WE 70 ns tWHDX Data Hold Time 10 ns tWHAX Write Recover Time 15 ns tWLQZ Output Disable Time from WE 75 ns tOLWH Output Disable Time from OE 100 ns tWHOX Output Enable Time from WE 5 ns tOHDX Output Enable Time from OE 5 ns tWLOL Output Enable Setup for WE 10 ns tWHOL O...

Page 29: ... tDVRL Data Delay after IORD 50 ns tIGHQX Data Hold following IORD 5 ns tIGLIGH IORD Pulse Width 65 ns tAVIGL Address Setup before IORD 25 ns tGHAX Address Hold following IORD 10 ns tCLIGL CE Setup before IORD 5 ns tCHIGH CE Hold following IORD 10 ns tRLIGL REG Setup before IORD 5 ns tRHIGH REG Hold following IORD 0 ns tIGLINL INPACK Delay falling from IORD 1 ns tIGHINH INPACK Delay Rising from IO...

Page 30: ...cess Write Timing Symbol Parameter Minimum Maximum Units tIGHDX Data Hold following IOWR 5 ns tIGHQX Data Setup before IOWR 20 ns tIGLIGH IOWR Pulse Width 65 ns tAVIGL Address Setup before IOWR 25 ns tAXIGH Address Hold following IOWR 10 ns tCLIGL CE Setup before IOWR 5 ns tCHIGH CE Hold following IOWR 10 ns tRLIGL REG Setup before IOWR 5 ns tRHIGH REG Hold following IOWR 0 ns tAVISL IOIS16 Delay ...

Page 31: ...ng Symbol Parameter Minimum Maximum Units tICL Cycle Time 100 ns tAVRWL Address Valid to DIOR DIOW Setup Time 15 ns tRWPW DIOR DIOW Pulse Width 65 ns tDVWL DIOW Data Setup Time 20 ns tDXWH DIOW Data Hold Time 5 ns tDVRL DIOR Data Setup Time 15 ns tDXRH DIOR Data Hold Time 5 ns tAV16L Address Valid to IOCS16 Assertion 1 ns tAX16H Address Valid to IOCS16 Negation 1 ns tAXRWH DIOW DIOR to Address Val...

Page 32: ...ve DMA disabled Figure 7 True IDE Multiword DMA Read Write Access Timing Table 17 True IDE Multiword DMA Read Write Access Timing Symbol Parameter Minimum Maximum Units tRWC Cycle Time mode 2 100 ns tRWPW DIOR DIOW Pulse Width 65 ns tRDA DIOR Data Access 50 ns tRWSU DIOR DIOW Data Setup Time 15 ns tWH DIOW Data Hold Time 5 ns tRH DIOR Data Hold Time 5 ns tDMRW DMACK to DIOR DIOW Setup Time 0 ns tR...

Page 33: ...te Memory Map on page 25 With respect to SiliconDrive CF attribute memory consists of two sections Card Information Structure CIS which contains a description of the Card s capabilities and specifications Function Configuration Registers FCRs which consists of four registers that can be read or written to by a host to configure the Card for specific purposes ATTRIBUTE MEMORY READ OPERATIONS Attrib...

Page 34: ...4 FEBRUARY 2 2009 ATTRIBUTE MEMORY WRITE OPERATIONS Attribute memory write operations are enabled by asserting REG WE and CE1 low Odd byte write operations from the attribute memory plane are not valid Table 19 Attribute Memory Write Operations Function Mode REG CE1 CE2 A0 OE WE D 15 8 D 7 0 Standby L H H X X X High Z High Z Byte Access L L H L H L High Z Even L H L H H L High Z Not Valid Word Acc...

Page 35: ... plane is comprised of two components the CIS and the FCRs The following tables detail the type location and read write requirements for each of the four FCRs maintained in the attribute memory plane Table 20 Attribute Memory Map Register Operation Addr CE1 REG WE OE Card Information Structure Read X 0 0 1 0 Write X 0 0 0 1 Configuration Option Read 200h 0 0 1 0 Write 200h 0 0 0 1 Card Configurati...

Page 36: ...ker 0Ah 1Ch CISTPL_DEVICE_OC Other conditions device in tuple code Tuple code 0Ch 04h TPL_LINK Link length is 4 bytes Link to next tuple 0Eh 02h EXT Reserved VCC MWAIT 3V wait is Not Used Other conditions information field 10h D9h Device Type W P S Device Speed Device type DH I O Device WPS 1 No WP Device speed 1 250ns 12h 01h 1x 2K units 2KB of address space Device size 14h FFh List End Marker En...

Page 37: ...ique serial number D 0 Single drive on Card Basic ATA option parameters byte 1 42h 07h R I E N P3 P2 P1 P0 P0 Sleep mode supported P1 Standby mode supported P2 Idle mode supported P3 Drive auto power control N Some configuration excludes 3X7 E Index bit is emulated I Twin IOIS16 data register only R Reserved Basic ATA option parameters byte 2 44h 1Ah CISTPL_CONFIG Configuration tuple Tuple code 46...

Page 38: ...I Powerdown current information PI Peak current information AI Average current information SI Static current information HV Maximum voltage information LV Minimum voltage information NV Nominal voltage information Power parameters for VCC 5Eh 55h X Mantissa Exponent Nominal voltage 5V VCC nominal value 60h 4Dh X Mantissa Exponent VCC nominal 4 5V VCC minimum value 62h 5Dh X Mantissa Exponent VCC n...

Page 39: ...um voltage information NV Nominal voltage information Power parameters for VCC 76h B5h X Mantissa Exponent Nominal voltage 3 0 V VCC nominal value 78h 1Eh Extension 0 3 V Extension byte 7Ah 4Dh X Mantissa Exponent Maximum average current over 10ms is 45 mA Maximum average current 7Ch 1Bh CISTPL_TABLE_ENTRY Configuration table entry tuple Tuple code 7Eh 0Dh TPL_LINK Link length is 10 bytes Link to ...

Page 40: ...n field TPCE_IO 92h F0h S P L M V B I N S 1 Share logic active P 1 Pulse mode IRQ supported L 1 Level mode IRQ supported M 1 Bit mask of IRQs present V 0 No vender unique IRQ B 0 No bus error IRQ I 0 No IO check IRQ N 0 No NMI Interrupt request description structure TPCE_IR 94h FFh IR IR IR IR IR IR IR IR SiliconSystems recommends the IRQ level to be routed 0 to 15 Mask extension byte 1 TPCE_IR Q ...

Page 41: ...current over 10ms is 45mA Maximum average current AAh 1Bh CISTPL_TABLE_ENTRY Configuration table entry tuple Extension byte ACh 12h TPL_LINK Link length is 18 bytes Link to next tuple AEh C2h I D Configuration Index ATA primary I O mapped configuration I 1 Interface byte follows D 1 default entry follows Configuration index 2 Configuration table index byte TPCE_INDX B0h 41h W R P B Interface Type ...

Page 42: ...I O length 1 First I O range length C8h F6h Second I O Base Address Second I O base address LSB Second I O range address CAh 03h Second I O Base Address Second I O base address MSB CCh 01h Second I O Range Length Second I O length 1 Second I O range length CEh EEh S P L M IRQ Level S 1 Share logic active P 1 Pulse mode IRQ supported L 1 Level mode IRQ supported M 0 Bit mask of IRQs present IRQ lev...

Page 43: ...nal value E0h 4Dh Extension 0 3V Extension byte E2h 1Bh CISTPL_TABLE_ENTRY Configuration table entry tuple Tuple code E4h 12h TPL_LINK Link length is 18 bytes Link to next tuple E6h C3h M MS IR IO T P M 0 No miscellaneous information MS 00 No memory space information IR 0 No interrupt information present IO 0 No I O port information present T 0 No timing information present P 1 VCC only informatio...

Page 44: ...8 bit hosts supported IO AddrLines 10 lines decoded I O space description field TPCE_IO F8h 61h LS AS N Range LS 1 Size of lengths is 1 byte AS 2 Size of address is 2 bytes N Range 1 Address range 1 I O range format description FAh 70h First I O base address LSB First I O range address FCh 01h First I O base address MSB FEh 07h First I O length 1 First I O range length 100h 76h Second I O base add...

Page 45: ...ltage information NV Nominal voltage information Power parameters for VCC 114h B5h X Mantissa Exponent Nominal voltage 3 0V VCC nominal value 116h 1Eh Extension 0 3V Extension byte 118h 4Dh X Mantissa Exponent Maximum average current over 10ms is 45mA Maximum average current 11Ah 1Bh CISTPL_MANFID Manufacturer s ID code Tuple code 11Ch 04h TPL_LINK Link length is 4 bytes Link to next tuple 11Eh 07...

Page 46: ...ll unauthorized use and or reproduction is prohibited 3100P 06DSR PAGE 36 FEBRUARY 2 2009 13Ch 4Fh O 13Eh 4Eh N 140h 53h S 142h 59h Y 144h 53h S 146h 54h T 45h E 14Ah 4Dh M 14Ch 53h S 14Eh 00h Space 150h 56h V 152h 45h E 154h 52h R 156h 32h 2 158h 2Eh 15Ah 30h 0 15Ch 30h 0 00h 160h FFh Table 21 Card Information Structure Continued Attribute Offset Data 7 6 5 4 3 2 1 0 Description of Contents CIS F...

Page 47: ... the SiliconDrive CF define the address decoding and initiate the software RESET sequence Table 22 Configuration Option Register 200h Operation D7 D6 D5 D4 D3 D2 D1 D0 Read Write SRESET LevIREQ Configuration Index Default Value 0 0 0 0 0 0 0 0 Bit s Description SRESET When set this bit initiates a software reset sequence which is equivalent to a power on reset or hardware reset LevlREQ IREQ interr...

Page 48: ...IOis8 0 0 PwrDn Int 0 Default Value 0 0 0 0 0 0 0 0 Bit s Description Changed Indicates that either CREADY D5 or CWPort D4 of the Pin Replacement register is set Additionally this bit changes state as the Powerdown D2 bit changes SigChg Outputs the inverse state of the Changed bit to the hardware interface signal STSCHG at the card interface Iois8 Informs the host of the valid data bus width for t...

Page 49: ...Y 2 2009 PIN PLACEMENT REGISTER 204H Table 24 Pin Placement Register 204h Operation D7 D6 D5 D4 D3 D2 D1 D0 Read Write CBVD1 CBVD2 CRDY CWProt RBVD1 RBVD2 RRDY RWProt Default Value 0 0 0 0 1 1 0 0 Bit s Description CRDY Indicates a bit change in the RRDY D1 bit CWProt Indicates a bit change in the RWProt D0 bit RRDY When set High 1 informs the host that the card is ready Low 0 state indicates the ...

Page 50: ...ket and Copy Register 206h Operation D7 D6 D5 D4 D3 D2 D1 D0 Read Write RFU Copy Number Socket Number Default Value 0 0 0 0 0 0 0 0 Bit s Description RFU Reserved for future use Copy Number Indicates the card number Allows the host to differentiate between identical cards by writing to the bit of the card that is being accessed This value is compared to the DRV bit in the ATA Drive Head register C...

Page 51: ... CE1 CE2 or both and OE low REG and WE must be inactive COMMON MEMORY WRITE OPERATIONS Common memory write operations are issued by asserting CE1 CE2 or both and WE low REG and OE must be inactive Table 26 Common Memory Read Operations Function Mode REG CE1 CE2 A0 OE WE D 15 8 D 7 0 Standby X H H X X X High Z High Z Byte Access H L H L L H High Z Even H L H H L H High Z Odd Word Access H L L X L H...

Page 52: ... OPERATIONS Table 28 I O Space Read Operations Function Mode REG CE1 CE2 A0 IORD IOWR D 15 8 D 7 0 Standby X H H X X X High Z High Z Byte Access L L H L L H High Z Even L L H H L H High Z Odd Word Access L L L L L H Odd Even I O Inhibit H X X X L H High Z High Z Odd Byte Only Access L H L X L H Odd High Z Table 29 I O Space Write Operations Function Mode REG CE1 CE2 A0 IORD IOWR D 15 8 D 7 0 Stand...

Page 53: ...A registers are mapped to common memory space in a 2KB window starting at address 0 Table 30 Memory Mapped Register Decoding Reg Offset A10 A9 A4 A3 A2 A1 A0 OE L WE L 1 0 0 X 0 0 0 0 Even Data Read Even Data Write 1 1 0 X 0 0 0 1 Error Feature 1 2 0 X 0 0 1 0 Sector Count Sector Count 1 3 0 X 0 0 1 1 Sector Number Sector Number 1 4 0 X 0 1 0 0 Cylinder Low Cylinder Low 1 5 0 X 0 1 0 1 Cylinder Hi...

Page 54: ... 31 Independent I O Mode Register Decoding Reg Offset A10 A9 A4 A3 A2 A1 A0 OE L WE L 0 0 X X 0 0 0 0 Even Data Read Even Data Write 0 1 X X 0 0 0 1 Error Feature 0 2 X X 0 0 1 0 Sector Count Sector Count 0 3 X X 0 0 1 1 Sector Number Sector Number 0 4 X X 0 1 0 0 Cylinder Low Cylinder Low 0 5 X X 0 1 0 1 Cylinder High Cylinder High 0 6 X X 0 1 1 0 Drive Head Drive Head 0 7 X X 0 1 1 1 Status Comm...

Page 55: ...ondary I O Mapped Register Decoding Reg A10 A9 A4 Primary A9 A4 Secondary A3 A2 A1 A0 IORD L IOWR L 0 X 1Fxh 17xh 0 0 0 0 Even Data Read Even Data Write 0 X 1Fxh 17xh 0 0 0 1 Error Feature 0 X 1Fxh 17xh 0 0 1 0 Sector Count Sector Count 0 X 1Fxh 17xh 0 0 1 1 Sector Number Sector Number 0 X 1Fxh 17xh 0 1 0 0 Cylinder Low Cylinder Low 0 X 1Fxh 17xh 0 1 0 1 Cylinder High Cylinder High 0 X 1Fxh 17xh 0...

Page 56: ... data in the SiliconDrive The decoded addresses are as shown in the following table Table 33 Task File Register Specification CS0 CS1 DA02 DA01 DA00 DIOR L DIOW L 0 1 0 0 0 Data Data 0 1 0 0 1 Error Feature 0 1 0 1 0 Sector Count Sector Count 0 1 0 1 1 Sector Number Sector Number 0 1 1 0 0 Cylinder Low Cylinder Low 0 1 1 0 1 Cylinder High Cylinder High 0 1 1 1 0 Drive Head Drive Head 0 1 1 1 1 Sta...

Page 57: ...if any generated from the last executed ATA command The contents are qualified by the ERR bit being set in Status Register on page 54 Table 34 Error Register Operation D7 D6 D5 D4 D3 D2 D1 D0 Read BBK UNC MC IDNF MCR ABRT TKNOF AMNF Default Value 0 0 0 0 0 0 0 0 Bit s Description 7 Bad Block Detected BBK Set when a bad block is detected 6 Uncorrectable Data Error UNC Set when an uncorrectable erro...

Page 58: ...onSystems Inc All unauthorized use and or reproduction is prohibited 3100P 06DSR PAGE 48 FEBRUARY 2 2009 FEATURE REGISTER The Feature register is command specific and used to enable and disable interface features This register supports only either odd or even byte data transfers Table 35 Feature Register Operation D7 D6 D5 D4 D3 D2 D1 D0 Read Write Feature Byte ...

Page 59: ...nSystems Inc All unauthorized use and or reproduction is prohibited 3100P 06DSR PAGE 49 FEBRUARY 2 2009 SECTOR COUNT REGISTER The Sector Count register is used to read or write the sector count of the data for which an ATA transfer has been made Table 36 Sector Count Register Operation D7 D6 D5 D4 D3 D2 D1 D0 Read Write Sector Count Default Value 0 0 0 0 0 0 0 1 ...

Page 60: ...xecuted Following a qualified ATA command sequence the device sets the register value to the last sector read or written as a result of the previous AT command When Logical Block Addressing LBA mode is implemented and the host issues a command the contents of the register describe the Logical Block Number bits A 7 0 Following an ATA command the device loads the register with the LBA block number r...

Page 61: ...ylinder Low register is set by the host to specify the cylinder number low byte Following an ATA command the content of the register is written by the device identifying the cylinder number low byte In LBA mode the 8 bit register maintains the contents of the Logical Block number address bits A15 A08 Table 38 Cylinder Low Register Operation D7 D6 D5 D4 D3 D2 D1 D0 Read Write Cylinder Number Low By...

Page 62: ...er High register is set by the host to specify the cylinder number high byte Following an ATA command the content of the register is set internally by the device identifying the cylinder number high byte In LBA mode the 8 bit register maintains the contents of the Logical Block number address bits A23 A16 Table 39 Cylinder High Register Operation D7 D6 D5 D4 D3 D2 D1 D0 Read Write Cylinder Number ...

Page 63: ... specify one of a pair of ATA drives present in the platform Table 40 Drive Head Register Operation D7 D6 D5 D4 D3 D2 D1 D0 Read Write 1 LBA 1 DRV HS3 LBA27 HS2 LBA26 HS1 LBA25 HS0 LBA24 Default Value 1 0 1 0 0 0 0 0 Bit s Description 6 LBA Selects between CHS 0 and LBA 1 addressing mode 4 Drive Address DRV Indicates the drive number selected by the host either 0 or 1 3 0 HS3 to 0 Indicates bits 3...

Page 64: ...Status Register Operation D7 D6 D5 D4 D3 D2 D1 D0 Read Write BSY DRDY DWF DSC DRQ CORR IDX ERR Default Value 0 0 0 0 0 0 0 0 Bit s Description 7 Busy BSY Set when the drive is busy and unable to process any new ATA commands 6 Data Ready DRDY Set when the device is ready to accept ATA commands from the host 5 Drive Write Fault DWF Always set to 0 4 Drive Seek Complete DSC Set when the drive heads h...

Page 65: ...100P 06DSR PAGE 55 FEBRUARY 2 2009 COMMAND REGISTER The Command register specifies the ATA command code being issued to the drive by the host Execution of the command begins immediately following the issuance of the command register code by the host See ATA Command Block and Set Description on page 59 for a listing of the supported ATA commands Table 42 Command Register Operation D7 D6 D5 D4 D3 D2...

Page 66: ...production is prohibited 3100P 06DSR PAGE 56 FEBRUARY 2 2009 ALTERNATE STATUS REGISTER The Alternate Status register is a read only register indicating the status of the device following the previous ATA command See Status Register on page 54 for specific details Table 43 Alternate Status Register Operation D7 D6 D5 D4 D3 D2 D1 D0 Read Write BSY DRDY DWF DSC DRQ CORR IDX ERR Default Value 0 0 0 0 ...

Page 67: ...ARY 2 2009 DEVICE CONTROL REGISTER The Device Control register is used to control the interrupt request and issue ATA software resets Table 44 Device Control Register Operation D7 D6 D5 D4 D3 D2 D1 D0 Write 1 SRST nIEN 0 Bit s Description 7 4 Reserved bits 3 Always set to 1 2 Software Reset SRST When set resets the ATA software 1 Interrupt Enable nIEN When set device interrupts are disabled There ...

Page 68: ...Device Address register is used to maintain compatibility with ATA disk drive interfaces Table 45 Device Address Register Operation D7 D6 D5 D4 D3 D2 D1 D0 Read Write nWTG nHS3 nHS2 nHS1 nHS0 nDS1 nDS0 Default Value 0 0 1 1 1 1 1 0 Bit s Description 7 Reserved bit 6 Write Gate nWTG Low when a write to the device is in process 5 2 nHS3 to nHS0 The negated binary address of the currently selected he...

Page 69: ...the ANSI standard ATA protocol A description of the ATA command block is provided in the following table ATA COMMAND SET Table 46 ATA Command Block and Set Description Operation D7 D6 D5 D4 D3 D2 D1 D0 Feature X Sector Count X Sector Number X Cylinder Low X Cylinder High X Drive Head 1 LBA 1 Drive X Command X Table 47 ATA Command Set Class Command Name Command Code Registers Used FR SC SN CY DH LB...

Page 70: ...used 1 Read Long Sector 22h 23h Y Y Y Y 1 Read Sector s 20h 21h Y Y Y Y 1 Read Verify Sector s 40h 41h Y Y Y Y Y 1 Recalibrate 1Xh Y 1 Request Sense 03h D 1 Seek 7Xh Y Y Y Y 1 Set Features EFh Y D 1 Set Multiple Mode C6h Y D 1 Set Sleep Mode 99h E6h D 1 Standby 96h E2h D 1 Standby Immediate 94h E0h D 1 Translate Sector 87h Y Y Y Y Y 1 Wear Level F5h Y 2 Write Buffer E8h D 1 Write DMA CAh Y Y Y Y Y...

Page 71: ...Power Mode command verifies the device s current power mode When the device is configured for standby mode or is entering or exiting standby the BSY bit is set the Sector Count register set to 00h and the BSY bit is cleared In idle mode BSY is set and the Sector Count register is set to FFh The BSY bit is then cleared and an interrupt is issued Table 48 Check Power Mode 98h E5h Register D7 D6 D5 D...

Page 72: ... 3100P 06DSR PAGE 62 FEBRUARY 2 2009 Executive Drive Diagnostic 90h The Executive Drive Diagnostic performs an internal read write diagnostic test using AA55h and 55AAh If an error is detected in the read write buffer the Error register reports the appropriate diagnostic code Table 49 Executive Drive Diagnostic 90h Register D7 D6 D5 D4 D3 D2 D1 D0 Feature X Sector Count X Sector Number X Cylinder ...

Page 73: ...use and or reproduction is prohibited 3100P 06DSR PAGE 63 FEBRUARY 2 2009 Format Track 50h The Format Track command formats the common solid state memory array Table 50 Format Track 50h Register D7 D6 D5 D4 D3 D2 D1 D0 Feature X Sector Count Sector Count Sector Number Sector Number LBA7 0 Cylinder Low Cylinder Low LBA15 8 Cylinder High Cylinder High LBA23 16 Drive Head 1 LBA 1 Drive Head Number LB...

Page 74: ...uction is prohibited 3100P 06DSR PAGE 64 FEBRUARY 2 2009 Identify Drive ECh Issued by the host the Identify Drive command provides 256 bytes of drive attribute data i e sector size count and so on The identify drive data structure is detailed in the following table Table 51 Identify Drive ECh Register D7 D6 D5 D4 D3 D2 D1 D0 Feature X Sector Count X Sector Number X Cylinder Low X Cylinder High X D...

Page 75: ...agnetic disk 14 Formatting speed latency permissible gap needed 13 Track Offset option supported 12 Data Strobe Offset option supported 11 Over 0 5 rotational speed difference 10 Disk transfer rate 10Mbps 9 10Mbps disk transfer rate 5Mbps 8 5Mbps disk transfer rate 7 Removable cartridge drive 6 Fixed drive 5 Spindle Motor Control option executed 4 Over 15μs changing head time 3 Non MFM encoding 2 ...

Page 76: ...0 ASCII characters 47 0001h 2 7 0 Maximum number of sectors that can be transferred with a Read Write Multiple command per interrupt 48 0000h 2 Double word 32 bit not supported 49 0002h 2 11 IORDY supported 9 LBA supported 8 DMA supported 50 0000h 2 Reserved 51 0100h 2 15 8 PIO data transfer cycle timing 52 0000h 2 15 8 DMA data transfer cycle timing 53 0000h 2 1 Words 64 70 are valid 0 Words 54 5...

Page 77: ...ultiword DMA modes supported 64 0003h 2 PIO modes supported 65 0078h 2 Minimum DMA transfer cycle time per word ns 66 0078h 2 Manufacturer s recommended DMA transfer cycle time ns 67 0078h 2 Minimum PIO transfer cycle time without flow control ns 68 0078h 2 Minimum PIO transfer cycle time with IORDY flow controls ns 69 127 0000h 118 Reserved 128 159 0000h 64 Vendor unique 160 255 0000h 192 Reserve...

Page 78: ...host the device s internal controller sets the BSY bit enters the Idle mode clears the BSY bit and generates an interrupt If the sector count is non zero it is interpreted as a timer count with each count being 5ms and the automatic power down mode is enabled If the sector count is zero the automatic power down mode is disabled Table 53 Idle 97h E3h Register D7 D6 D5 D4 D3 D2 D1 D0 Feature X Secto...

Page 79: ...ibited 3100P 06DSR PAGE 69 FEBRUARY 2 2009 Idle Immediate 95h E1h When issued by the host the device s internal controller sets the BSY bit enters Idle Mode clears the BSY bit and issues an interrupt The interrupt is issued whether or not the Idle mode is fully entered Table 54 Idle Immediate 95h E1h Register D7 D6 D5 D4 D3 D2 D1 D0 Feature X Sector Count X Sector Number X Cylinder Low X Cylinder ...

Page 80: ...ve Parameters 91h Initialize Drive Parameters allows the host to set the sector counts per track and the head counts per cylinder to 1 Fixed Upon issuance of the command the device sets the BSY bit and associated parameters clears the BSY bit and issues an interrupt Table 55 Initialize Drive Parameters 91h Register D7 D6 D5 D4 D3 D2 D1 D0 Feature X Sector Count Sector Count Number of Sectors Secto...

Page 81: ...se and or reproduction is prohibited 3100P 06DSR PAGE 71 FEBRUARY 2 2009 Recalibrate 1Xh The Recalibrate command sets the cylinder low and high head number to 0h and sector number to 1h in CHS mode In LBA mode i e LBA 1 the sector number is set to 0h Table 56 Recalibrate 1Xh Register D7 D6 D5 D4 D3 D2 D1 D0 Feature X Sector Count X Sector Number X Cylinder Low X Cylinder High X Drive Head 1 LBA 1 ...

Page 82: ... Read Buffer E4h The Read Buffer command allows the host to read the contents of the sector buffer When issued the device sets the BSY bit and sets up the sector buffer data in preparation for the read operation When the data is ready the DRQ bit is set and the BSY bit in the Status register are set and cleared respectively Table 57 Read Buffer E4h Register D7 D6 D5 D4 D3 D2 D1 D0 Feature X Sector...

Page 83: ...100P 06DSR PAGE 73 FEBRUARY 2 2009 Read DMA C8h The Read DMA command allows the host to read data using the DMA transfer protocol Note This function does not apply to SiliconDrives that have DMA disabled Table 58 Read DMA C8h Register D7 D6 D5 D4 D3 D2 D1 D0 Feature X Sector Count Sector Count Sector Number Sector Number LBA7 0 Cylinder Low Cylinder Low LBA15 8 Cylinder High Cylinder High LBA23 16...

Page 84: ...ad Multiple C4h The Read Multiple command executes similarly to the Read Sector command with the exception that interrupts are issued only when a block containing the counts of sectors defined by the Set Multiple command is transferred Table 59 Read Multiple C4h Register D7 D6 D5 D4 D3 D2 D1 D0 Feature X Sector Count Sector Count Sector Number Sector Number LBA7 0 Cylinder Low Cylinder Low LBA15 8...

Page 85: ... count is set to 0h all 256 sectors of data are made available When the command code is issued and the first sector of data has been transferred to the buffer the DRQ bit is set The Read Sector command is terminated by writing the cylinder head and sector number of the last sector read in the task file On error the read operation is aborted in the errant sector Table 60 Read Sector 20h 21h Registe...

Page 86: ...he Read Long Sector s command operates similarly to the Read Sector s command with the exception that it transfers requested data sectors and ECC data The long instruction ECC byte transfer for Long commands is a byte transfer at a fixed length of 4 bytes Table 61 Read Long Sector s 22h 23h Register D7 D6 D5 D4 D3 D2 D1 D0 Feature X Sector Count X Sector Number Sector Number LBA7 0 Cylinder Low Cy...

Page 87: ...ector s command operates similarly to the Read Sector s command with the exception that is does not set the DRQ bit and does not transfer data to the host When the requested sectors are verified the onboard controller clears the BSY bit and issues an interrupt Table 62 Read Verify Sector s 40h 41h Register D7 D6 D5 D4 D3 D2 D1 D0 Feature X Sector Count Sector Count Sector Number Sector Number LBA7...

Page 88: ...RY 2 2009 Seek 7Xh The Seek command seeks and picks up the head to the tracks specified in the task file When the command is issued the solid state memory chips do not need to be formatted After an appropriate amount of time the DSC bit is set Table 63 Seek 7Xh Register D7 D6 D5 D4 D3 D2 D1 D0 Feature X Sector Count X Sector Number Sector Number LBA7 0 Cylinder Low Cylinder Low LBA15 8 Cylinder Hi...

Page 89: ...e set of the device according to the attributes listed in Table 65 On power up or following a hardware reset the device is set to the default mode 81h Table 64 Set Features EFh Register D7 D6 D5 D4 D3 D2 D1 D0 Feature Feature Sector Count X Sector Number X Cylinder Low X Cylinder High X Drive Head X X X Drive X Command EFh Table 65 Set Features Attributes Feature Operation 01h Enable 8 bit data tr...

Page 90: ...iple Mode C6h The Set Multiple Mode command allows the host to access the drive via Read Multiple and Write Multiple ATA commands Additionally the command sets the block count i e the number of sectors within the block for the Read Write Multiple command The sector count per block is set in the Sector Count register Table 66 Set Multiple Mode C6h Register D7 D6 D5 D4 D3 D2 D1 D0 Feature X Sector C...

Page 91: ...Set Sleep Mode 99h E6h The Set Sleep Mode command allows the host to set the device in sleep mode When the onboard controller transitions to sleep mode it clears the BSY bit and issues an interrupt The device interface then becomes inactive Sleep mode can be exited by issuing either a hardware or software reset Table 67 Set Sleep Mode 99h E6h Register D7 D6 D5 D4 D3 D2 D1 D0 Feature X Sector Count...

Page 92: ...PAGE 82 FEBRUARY 2 2009 Standby 96h E2h When the Standby command is issued by the host it transitions the device into standby mode If the Sector Count register is set to a value other than 0h the Auto Powerdown function is enabled and the device returns to Idle mode Table 68 Standby 96h E2h Register D7 D6 D5 D4 D3 D2 D1 D0 Feature X Sector Count Timer Count 5ms x Timer Count Sector Number X Cylind...

Page 93: ...All unauthorized use and or reproduction is prohibited 3100P 06DSR PAGE 83 FEBRUARY 2 2009 Standby Immediate 94h E0h When the Standby Immediate command is issued by the host it transitions the device into standby mode Table 69 Standby Immediate 94h E0h Register D7 D6 D5 D4 D3 D2 D1 D7 Feature X Sector Count X Sector Number X Cylinder Low X Cylinder High X Drive Head X X X Drive X Command 94h or E0...

Page 94: ...s Inc All unauthorized use and or reproduction is prohibited 3100P 06DSR PAGE 84 FEBRUARY 2 2009 Write Buffer E8h The Write Buffer command allows the host to rewrite the contents of the 512 byte data buffer with the wanted data Table 70 Write Buffer E8h Register D7 D6 D5 D4 D3 D2 D1 D7 Feature X Sector Count X Sector Number X Cylinder Low X Cylinder High X Drive Head X X X Drive X Command E8h ...

Page 95: ...0P 06DSR PAGE 85 FEBRUARY 2 2009 Write DMA CAh The Write DMA command allows the host to write data using the DMA transfer protocol Note This function does not apply to SiliconDrives that have DMA disabled Table 71 Write DMA CAh Register D7 D6 D5 D4 D3 D2 D1 D0 Feature X Sector Count Sector Count Sector Number Sector Number LBA7 0 Cylinder Low Cylinder Low LBA15 8 Cylinder High Cylinder High LBA23 ...

Page 96: ...Multiple command operates in the same manner as the Write Sector command When issued the device sets the BSY bit within 400ns and generates an interrupt at the completion of a transferred block of sectors The DRQ bit is set at the beginning of a block transfer Table 72 Write Multiple C5h Register D7 D6 D5 D4 D3 D2 D1 D0 Feature X Sector Count Sector Count Sector Number Sector Number LBA7 0 Cylinde...

Page 97: ...to 256 sectors as specified in the Sector Count register A sector count of 0 requests 256 sectors When issued the device sets the BSY bit within 400ns and generates an interrupt at the completion of a transferred block of sectors The DRQ bit is set at the beginning of a block transfer Table 73 Write Sector s 30h 31h Register D7 D6 D5 D4 D3 D2 D1 D0 Feature X Sector Count Sector Count Sector Number...

Page 98: ...ector s command operates in the same manner as the Write Sector command when issued the device sets the BSY bit within 400ns and generates an interrupt at the completion of a transferred block of sectors The DRQ bit is set at the beginning of a block transfer Table 74 Write Long Sector s 32h 33h Register D7 D6 D5 D4 D3 D2 D1 D0 Feature X Sector Count Sector Count Sector Number Sector Number LBA7 0...

Page 99: ...s prohibited 3100P 06DSR PAGE 89 FEBRUARY 2 2009 Erase Sector s C0h The Erase Sector s command is issued prior to the issuance of a Write Sector s or Write Multiple w o Erase command Table 75 Erase Sector s C0h Register D7 D6 D5 D4 D3 D2 D1 D0 Feature X Sector Count Sector Count Sector Number Sector Number LBA7 0 Cylinder Low Cylinder Low LBA15 8 Cylinder High Cylinder High LBA23 16 Drive Head X L...

Page 100: ...ined in the following table Table 76 Request Sense 03h Register D7 D6 D5 D4 D3 D2 D1 D0 Feature X Sector Count X Sector Number X Cylinder Low X Cylinder High X Drive Head 1 X 1 Drive X Command 03h Table 77 Extended Error Codes Extended Error Codes Description 00h No error detected 01h Self test is OK no error 09h Miscellaneous error 20h Invalid command 21h Invalid address requested head or sector ...

Page 101: ... FEBRUARY 2 2009 Translate Sector 87h The Translate Sector command is not currently supported by the SiliconSystems SiliconDrive If the host issues this command the device responds with 0x00h in the data register Table 78 Translate Sector 87h Register D7 D6 D5 D4 D3 D2 D1 D0 Feature X Sector Count Sector Count Sector Number Sector Number LBA7 0 Cylinder Low Cylinder Low LBA15 8 Cylinder High Cylin...

Page 102: ...on is prohibited 3100P 06DSR PAGE 92 FEBRUARY 2 2009 Wear Level F5h The Wear Level command is supported as an NOP command for the purposes of backward compatibility with the ANSI AT attachment standard This command sets the Sector Count register to 0x00h Table 79 Wear Level F5h Register D7 D6 D5 D4 D3 D2 D1 D0 Feature X Sector Count Completion Status Sector Number X Cylinder Low X Cylinder High X ...

Page 103: ...Multiple w o Erase CDh The Write Multiple w o Erase command functions identically to the Write Multiple command with the exception that the implied pre erase i e Erase Sector s command is not issued prior to writing the sectors Table 80 Write Multiple w o Erase CDh Register D7 D6 D5 D4 D3 D2 D1 D0 Feature X Sector Count Sector Count Sector Number Sector Number LBA7 0 Cylinder Low Cylinder Low LBA1...

Page 104: ...te Sector s w o Erase 38h The Write Sector s w o Erase command functions similar to the Write Sector command with the exception that the implied pre erase i e Erase Sector s command is not issued prior to writing the sectors Table 81 Write Sector s w o Erase 38h Register D7 D6 D5 D4 D3 D2 D1 D0 Feature X Sector Count Sector Count Sector Number Sector Number LBA7 0 Cylinder Low Cylinder Low LBA15 8...

Page 105: ...RY 2 2009 Write Verify 3Ch The Write Verify command verifies each sector immediately after it is written This command performs identically to the Write Sector s command with the added feature of verifying each sector written Table 82 Write Verify 3Ch Register D7 D6 D5 D4 D3 D2 D1 D0 Feature X Sector Count Sector Count Sector Number Sector Number LBA7 0 Cylinder Low Cylinder Low LBA15 8 Cylinder Hi...

Page 106: ...ORT To order or obtain information on pricing and delivery contact your SiliconSystems Sales Representative PART NUMBERING NOMENCLATURE The following table defines the SiliconDrive PC Card part numbering scheme Table 83 Part Numbering Nomenclature SSD P YYY T 3100 Part number suffix contact your SiliconSystems Sales Representative Temperature Range Blank Commercial I Industrial Capacity 32M 32MB t...

Page 107: ...MBERS The following table lists the SiliconDrive s part numbers SAMPLE LABEL Figure 8 Sample Label Table 84 Part Numbers Part Number Capacity SSD P16G I 3100 16GB SSD P08G I 3100 8GB SSD P04G I 3100 4GB SSD P02G I 3100 2GB SSD P01G I 3100 1GB SSD P51M I 3100 512MB SSD P25M I 3100 256MB SSD P12M I 3100 128MB SSD P64M I 3100 64MB SSD P32M I 3100 32MB Front Label Standard Back Label with Lot Code Inf...

Page 108: ...ems makes no representations or warranties regarding this document The names of actual companies and products mentioned herein are the trademarks of their respective owners SiliconSystems SiliconDrive SiliconDrive II SiSecure SiliconDrive EP PowerArmor SiSMART SiKey SiZone SiProtect SiSweep SiPurge SiScrub SiliconDrive USB Blade SolidStor and the SiliconSystems logo are trademarks or registered tr...

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