Si5381/82 Evaluation Board User's Guide
The Si5381/82A-E-EB is used for evaluating the Ultra-Low Phase
Noise Quad/Dual PLL. The Si5381/82 employs fourth-generation
DSPLL technology to enable clock generation for LTE/ JESD204B
applications which require the highest level of jitter performance.
The Si5381/82A-E-EB has four independent input clocks and a to-
tal of 12 outputs with 4/2 PLLs. The Si5381/82A-E-EB also has
four independent input clocks and a total of 12 outputs with 2
PLLs. The Si5381/82A-E-EB can be easily controlled and config-
ured using Silicon Labs’ Clock Builder Pro™ (CBPro™) software
tool.
The device revision is distinguished by a white 1 inch x 0.187 inch label with the text
“Si5381/82A-E-EB” installed in the lower left hand corner of the board. (For ordering pur-
poses only, the terms “EB” and “EVB” refer to the board and the kit respectively. For the
purpose of this document, the terms are synonymous in context.)
EVB FEATURES
• Powered from USB port or external power
supply
• Onboard 54 MHz XO provides holdover
mode of operation on the Si5381/82
• CBPro GUI programmable VDDO supplies
allow each of the ten primary outputs to
have its own supply voltage selectable
from 3.3, 2.5, or 1.8 V
• CBPro GUI-controlled voltage, current,
and power measurements of VDD and all
VDDO supplies
• Status LEDs for power supplies and
control/status signals of Si5381/82
• SMA connectors for input clocks and
output clocks
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