6.6.1 Verify Free-Run Mode Operation
Assuming no external clocks have yet been connected to the INPUT CLOCK differential SMA connectors, labeled “INx/INxB” and loca-
ted around the perimeter of the EVB, the DUT should now be operating in free-run mode and locked to the onboard XO.
You can run a quick check to determine if the device is powered up, generating output clocks, and consuming power by clicking on the
“
Read All
” button highlighted above and then reviewing the voltage, current and power readings for each VDDx supply.
Note:
Turning V
DD
or V
DDA
“Off” will power-down and reset the DUT. Once both of these supplies are turned “On” again, you must
reload the desired frequency plan back into the device memory by selecting the “
Write Design to EVB
” button on the CBPro home
screen:
Figure 6.12. CBPro—Write Design Button
Failure to do the step above will cause the device to read in the preprogrammed plan from its non-volatile memory (NVM).
However, the plan loaded from the NVM may not be the latest plan recommended by Silicon Labs for evaluation.
At this point, you should verify the presence and frequencies of the output clocks, running in free-run mode from the XO, using external
instrumentation connected to the output clock SMA connectors, labeled OUTx/OUTs. To verify plan inputs, go to the appropriate config-
uration page or click on “
Frequency Plan Valid
” to see the design report.
Figure 6.13. CBPro—Design Report Button and Link
Si5381/82 Evaluation Board User's Guide
Using the Si5381/82A-E-EVB and Installing ClockBuilderPro (CBPro) Desktop Software
silabs.com
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