Rev. 0.6 1/12
Copyright © 2012 by Silicon Laboratories
Si536x-EVB
S i 5 3 6 5 / 6 6 - E V B
S i 5 3 6 7 / 6 8 - E V B
S i 5 3 6 9 - E V B
S i 5 3 6 5 / 6 6 / 6 7 / 6 8 / 6 9 E
V A L U A T I O N
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O A R D
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1. Introduction
The Si5365/66-EVB,Si5367/68-EVB, and Si5369-EVB provide platforms for evaluating Silicon Laboratories'
Si5365/Si5366, Si5367/Si5368, and Si5369 Any-Frequency Precision Clocks. The Si5365 and Si5366 are
controlled directly using configuration pins on the devices, while the Si5367, Si5368, and Si5369 are controlled by
a microprocessor or MCU (microcontroller unit) via an I
2
C or SPI interface. The Si5365 and Si5367 are low jitter
clock multipliers with a loop bandwidth ranging from 30 kHz to 1.3 MHz. The Si5366 and Si5368 are jitter-
attenuating clock multipliers, with a loop bandwidth ranging from 60 Hz to 8.4 kHz. The Si5369 is similar to the
Si5368, with a much lower loop BW of from 4 to 525 Hz. The Si5366 device can optionally be configured to operate
as a Si5365, so a single evaluation board is available to evaluate both devices. Likewise, the Si5368 can be
configured to operate as a Si5367, so the two devices share a single evaluation board.
The Si5365/66/67/68/69 Any-Frequency Precision Clocks are based on Silicon Laboratories' 3rd-generation
DSPLL
®
technology, which provides any-frequency synthesis in a highly integrated PLL solution that eliminates the
need for external VCXO and loop filter components. The devices have excellent phase noise and jitter
performance. The Si5366, Si5368, and Si5369 jitter attenuating clock multipliers support jitter generation of 0.3 ps
RMS (typ) across the 12 kHz–20 MHz and 50 kHz–80 MHz jitter filter bandwidths. The Si5365 and SI5367 support
jitter generation of 0.6 ps RMS (typ) across the 12 kHz–20 MHz and 50 kHz–80 MHz jitter filter bandwidths. For all
devices, the DSPLL loop bandwidth is digitally programmable, providing jitter performance optimization at the
application level. These devices are ideal for providing clock multiplication/clock division, jitter attenuation, and
clock distribution in mid-range and high performance timing applications.
Figure 1. Si536x TQFP EVB
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