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Silicon Laboratories Si5340, Manual

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S i 5 3 4 1 / 4 0

46

Preliminary Rev. 0.9

A

PPENDIX

—A

DVANCE

 P

RODUCT

 I

NFORMATION

 R

EVISION

 H

ISTORY

Table 21 lists the advance product information revision history.

Table 21. Advance Product Information Revision History

Revision

Change Description

Date

0.11

First draft

Aug 2012

0.12

Added clarification to section 1 on unused control inputs, unused clock inputs, and 

pull-up resistors for the I

2

C interface.

Aug 2012

0.13

Updated block diagram

Other minor edits

Dec 2012

0.20

Updated pinouts, block diagrams, and electrical specifications

Programmable status pins (S0-S3) have been assigned to LOS status pins

Added register map information

Added package outline, land patterns, ordering guide, top markings

Reduced MultiSynth from 10 to 5

Combined Si5341 and Si5340 data sheets

Added application diagram

Jun 2013

0.21

Minor updates from review cycle

Added new SPI streaming command

Added SPI timing diagrams

Added high level register map 

July 2013

0.22

Minor edits

July 2013

0.23

Changed FINC/FDEC frequency step resolution from 0.05 ppb/step to 0.01 ppb/
step. 

Added REFCLK max input voltage swing specification of 1200 mVpp_se

Si5341 pin changes:



Renamed pin 13: VDD33 to VDDA



Renamed pins 32, 46, 60: VDD18 to VDD



Removed LOS0 function on pin 20. Renamed pin 20 to RSVD.



Removed LOS1 function on pin 21. Renamed pin 21 to RSVD.



Removed LOS2 function on pin 58.



Removed LOS_XAXB on pin 59. 



Moved OUT9 from 55 to 58. Renamed pin 55 to RSVD



Moved OUT9 from 56 to 59. Renamed pin 56 to RSVD

Si5340 pin changes:



Renamed pins 8, 9: VDD33 to VDDA



Renamed pins 21, 32, 39, 40: VDD18 to VDD



Renamed pin 26: VDD18 to VDDS

Other minor edits

Oct 2013

0.24

Updated Section 9 - Ordering Guide

Oct 2013

0.25

Minor edits

Oct 2013

Summary of Contents for Si5340

Page 1: ...MOS 100 Hz to 250 MHz Output output skew 100 ps Adjustable output output delay Optional zero delay mode Independent glitchless on the fly output frequency changes DCO mode with frequency increment and decrement as low as 0 001 ppb step Core voltage VDD 1 8 V 5 VDDA 3 3 V 5 Independent output supply pins 3 3V 2 5V or 1 8V Built in power supply filtering Status monitoring LOS LOL Serial Interface I2...

Page 2: ...i5341 40 FB_IN IN0 IN_SEL IN1 IN2 XB XA XTAL INT INT INT OSC Multi Synth OUT0 INT OUT1 INT OUT2 INT OUT3 INT OUT4 INT OUT5 INT OUT6 INT OUT7 INT OUT8 INT OUT9 INT Multi Synth Multi Synth Multi Synth Multi Synth Si5340 Si5341 PLL INT NVM I2 C SPI Control Status ...

Page 3: ... 6 Power Management 29 4 7 In Circuit Programming 29 4 8 Serial Interface 29 4 9 Custom Factory Preprogrammed Parts 29 5 Register Map 30 5 1 Addressing Scheme 30 5 2 High Level Register Map 30 6 Pin Descriptions 32 7 Ordering Guide 39 8 Package Outlines 40 8 1 Si5341 9x9 mm 64 QFN Package Diagram 40 8 2 Si5340 7x7 mm 44 QFN Package Diagram 41 9 PCB Land Pattern 42 10 Top Marking 44 11 Device Errat...

Page 4: ...ip XA XB 25 MHz 4x 200 MHz 2 5V LVCMOS 2x 161 1328125 MHz LVDS 2x 133 33 MHz 1 8V LVCMOS Buffer 125 MHz Level Translator Buffer Delay Line 4x 125 MHz 3 3V LVCMOS 3x 125 MHz LVPECL Si5341 Nn0 Nd0 LPF PD PLL Mn Md Free Run Mode OSC Nn1 Nd1 t2 N2n N2d N3n N3d N4n N4d 161 1328125MHz 133 33MHz 125MHz XA XB 125MHz 200MHz 1x 161 1328125 MHz LVDS 1x 161 1328125 MHz LVDS 2x 133 33 MHz 1 8V LVCMOS 2x 125 MH...

Page 5: ... 140 mA IDDA 115 125 mA Output Buffer Supply Current IDDOx LVPECL Output3 156 25 MHz 23 25 mA LVDS Output3 156 25 MHz 16 18 mA 3 3V LVCMOS4 output 156 25 MHz 19 26 mA 2 5 V LVCMOS4 output 156 25 MHz 15 19 mA 1 8 V LVCMOS4 output 156 25 MHz 11 13 mA Total Power Dissipation Pd Si5341 Notes 1 5 836 945 mW Si5340 Notes 2 5 645 mW Notes 1 Si5341 test configuration 7 x 2 5 V LVDS outputs enabled 156 25 ...

Page 6: ... Input Frequency fIN_CMOS 10 250 MHz Input Voltage VIL 0 1 0 33 V VIH 0 80 V Slew Rate1 2 SR 400 V µs Duty Cycle DC Clock Input 40 60 Minimum Pulse Width PW Pulse Input 1 6 ns Input Resistance RIN 8 kΩ REFCLK Applied to XA XB REFCLK Frequency fIN_REF Frequency range for best output jitter performance 48 54 MHz 10 120 MHz Input Voltage Swing VIN 350 1600 mVpp_se Slew rate1 2 SR Imposed for best jit...

Page 7: ...ons VDD 1 8 V 5 VDDA 3 3V 5 VDDO 1 8 V 5 2 5 V 5 or 3 3 V 5 TA 40 to 85 C Parameter Symbol Test Condition Min Typ Max Units Output Frequency fOUT 0 0001 800 MHz Duty Cycle DC f 400 MHz 48 52 400 MHz f 800 MHz 45 55 Output Output Skew TSK Differential Output 100 ps OUT OUT Skew TSK_OUT Measured from the positive to negative output pins 100 ps Notes 1 Normal swing mode high swing mode Vswing and Cmo...

Page 8: ...Table 5 Differential Clock Output Specifications Continued VDD 1 8 V 5 VDDA 3 3V 5 VDDO 1 8 V 5 2 5 V 5 or 3 3 V 5 TA 40 to 85 C Parameter Symbol Test Condition Min Typ Max Units Notes 1 Normal swing mode high swing mode Vswing and Cmode settings are programmable through register settings and can be stored in NVM Each output driver can be programmed independently 2 Not all combinations of voltage ...

Page 9: ...i5340 Status Output Pins LOL LOS_XAXB Output Voltage VOH IOH 2 mA VDDS x 0 85 V VOL IOL 2 mA VDDS x 0 15 V Note VDDIO is determined by the IO_VDD_SEL bit It is selectable as VDDA or VDD Table 5 Differential Clock Output Specifications Continued VDD 1 8 V 5 VDDA 3 3V 5 VDDO 1 8 V 5 2 5 V 5 or 3 3 V 5 TA 40 to 85 C Parameter Symbol Test Condition Min Typ Max Units Notes 1 Normal swing mode high swin...

Page 10: ... V CMOS2 IOH 12 mA CMOS3 IOH 17 mA VDDO 2 5 V CMOS1 IOH 6 mA VDDO x 0 85 V CMOS2 IOH 8 mA CMOS3 IOH 11 mA VDDO 1 8 V CMOS1 IOH 3 mA VDDO x 0 85 V CMOS2 IOH 4 mA CMOS3 IOH 5 mA Notes 1 Driver strength is a register programmable setting and stored in NVM Options are CMOS1 CMOS2 CMOS3 2 IOL IOH is measured at VOL VOH as shown in the DC test configuration 3 A series termination resistor Rs is recommen...

Page 11: ... 7 LVCMOS Clock Output Specifications Continued VDD 1 8 V 5 VDDA 3 3 V 5 VDDO 1 8 V 5 2 5 V 5 or 3 3 V 5 TA 40 to 85 C Parameter Symbol Test Condition Min Typ Max Units Notes 1 Driver strength is a register programmable setting and stored in NVM Options are CMOS1 CMOS2 CMOS3 2 IOL IOH is measured at VOL VOH as shown in the DC test configuration 3 A series termination resistor Rs is recommended to ...

Page 12: ...les Integer or Fractional Mode2 3 Measured in the time domain Performance is limited by the noise floor of the equipment 7 3 ps pk pk JCC 8 1 ps pk Jitter Generation Locked to External XTAL XTAL Frequency 48 MHz to 54 MHz JRMS Integer Mode2 12 kHz to 20 MHz 0 100 0 160 ps RMS Fractional DCO Mode3 12 kHz to 20 MHz 0 140 0 350 ps RMS JPER Derived from integrated phase noise 0 150 ps pk pk JCC 0 270 ...

Page 13: ... period of the SCL clock tLOW 4 7 1 3 µs HIGH period of the SCL clock tHIGH 4 0 0 6 µs Set up time for a repeated START condition tSU STA 4 7 0 6 µs Data hold time tHD DAT 5 0 µs Data set up time tSU DAT 250 100 ns Rise time of both SDA and SCL sig nals tr 1000 20 300 ns Fall time of both SDA and SCL sig nals tf 300 300 ns Set up time for STOP condition tSU STO 4 0 0 6 µs Bus free time between a S...

Page 14: ...Si5341 40 14 Preliminary Rev 0 9 Figure 2 I2C Serial Port Timing Standard and Fast Modes ...

Page 15: ...ll Time Tr Tf 10 ns SCLK High Low Time THL SCLK Period TC 50 ns Delay Time SCLK Fall to SDO Active TD1 12 5 ns Delay Time SCLK Fall to SDO TD2 12 5 ns Delay Time CS Rise to SDO Tri State TD3 12 5 ns Setup Time CS to SCLK TSU1 25 ns Hold Time CS to SCLK Rise TH1 25 ns Setup Time SDI to SCLK Rise TSU2 12 5 ns Hold Time SDI to SCLK Rise TH2 12 5 ns Delay Time Between Chip Selects CS TCS 50 ns SCLK CS...

Page 16: ...40 Family Reference Manual to determine ESR Crystal Frequency Range fXTAL_25 25 MHz Load Capacitance CL_25 8 pF Shunt Capacitance CO_25 3 pF Crystal Drive Level dL_25 200 µW Equivalent Series Resistance rESR_25 Refer to the Si5341 40 Family Reference Manual to determine ESR Notes 1 The Si5341 40 is designed to work with crystals that meet the specifications in Table 11 2 Refer to the Si5341 40 Fam...

Page 17: ...Thermal Resistance Junction to Board JB 9 4 JB 9 3 Thermal Resistance Junction to Top Center JT 0 2 Si5340 44QFN Thermal Resistance Junction to Ambient JA Still Air 22 3 C W Air Flow 1 m s 19 4 Air Flow 2 m s 18 4 Thermal Resistance Junction to Case JC 10 9 Thermal Resistance Junction to Board JB 9 3 JB 9 2 Thermal Resistance Junction to Top Center JT 0 23 Note Based on PCB Dimension 3 x 4 5 PCB T...

Page 18: ...5 to 150 C Junction Temperature TJCT 55 to 150 C Soldering Temperature Pb free profile 5 TPEAK 260 C Soldering Temperature Time at TPEAK Pb free profile 5 TP 20 40 sec Notes 1 Permanent device damage may occur if the absolute maximum ratings are exceeded Functional operation should be restricted to the conditions as specified in the operational sections of this data sheet Exposure to absolute maxi...

Page 19: ...R1 OUT0 VDDO0 OUT0 OUT2 VDDO2 OUT2 OUT3 VDDO3 OUT3 OUT4 VDDO4 OUT4 OUT5 VDDO5 OUT5 OUT6 VDDO6 OUT6 OUT7 VDDO7 OUT7 OUT8 VDDO8 OUT8 OUT9 VDDO9 OUT9 OUT1 VDDO1 OUT1 Pfb LPF PD Mn Md PLL IN_SEL 1 0 XA XB 25MHz 48 54MHz XTAL Free Run Mode Synchronous Mode P2 P1 P0 IN0 IN0 IN1 IN1 IN2 IN2 FDEC FINC Frequency Control N0n N0d t0 N2n N2d N3n N3d N4n N4d t2 t3 t4 N1n N1d t1 MultiSynth SYNC Dividers Drivers...

Page 20: ...OSXAB SDA SDIO A1 SDO SCLK A0 CS I2C_SEL SPI I2 C NVM Status Monitors MultiSynth R0 R2 R3 R1 OUT0 VDDO0 OUT0 OUT2 VDDO2 OUT2 OUT3 VDDO3 OUT3 OUT1 VDDO1 OUT1 Dividers Drivers Zero Delay Mode FB_IN FB_IN Pfb IN_SEL 1 0 Synchronous Mode P2 P1 P0 IN0 IN0 IN1 IN1 IN2 IN2 XA XB 25MHz 48 54MHz XTAL Free Run Mode OSC PREF Si5340 Generator Clock VDD VDDA 4 2 ...

Page 21: ...This clock generator is fully configurable via its serial interface I2 C SPI and includes in circuit programmable non volatile memory 4 1 Modes of Operation The Si5341 40 supports both free run and synchronous modes of operation Mode selection is manually selected through input pins IN_SEL0 1 or through the serial interface by writing to the input select register IN_SEL 0x21 2 1 Pin selection is s...

Page 22: ...us reference to the MultiSynth high performance fractional dividers A crosspoint mux connects any of the MultiSynth divided frequencies to any of the outputs drivers Additional output integer dividers provides further frequency division if required The frequency configuration of the device is programmed by setting the input dividers P the PLL feedback fractional divider Mn Md the MultiSynth fracti...

Page 23: ...ntial signals must be AC coupled while single ended LVCMOS signals can be AC or DC coupled Unused inputs can be disabled by register configuration Figure 8 Termination of Differential and LVCMOS Input Signals XO 100 Differential XO Connection 2xCL 2xCL XB XA OSC 2xCL 2xCL XB XA OSC XO Single ended XO Connection Crystal Resonator Connection OSC XB XA XTAL 2xCL 2xCL PREF PREF PREF DC Coupled LVCMOS ...

Page 24: ...he status monitors are accessible by reading registers through the serial interface or with dedicated pin LOL Each of the status indicator register bits has a corresponding sticky bit in a separate register location Once a status bit is asserted its corresponding sticky bit will remain asserted until cleared Writing a logic zero to a sticky register bit clears its state 4 4 2 Interrupt pin INTR An...

Page 25: ...ntial output swing modes Normal and High Each output can support a unique mode Differential Normal Swing Mode When an output driver is configured in normal swing mode its output swing is selectable as one of 7 settings ranging from 200 mVpp_se to 800 mVpp_se in increments of 100 mV The output impedance in the Normal Swing Mode is 100 differential Any of the terminations shown in Figure 10 are supp...

Page 26: ...5 4 5 7 LVCMOS Output Signal Swing The signal swing VOL VOH of the LVCMOS output drivers is set by the voltage on the VDDO pins Each output driver has its own VDDO pin allowing a unique output voltage swing for each of the LVCMOS drivers 4 5 8 LVCMOS Output Polarity When a driver is configured as an LVCMOS output it generates a clock signal on both pins OUTx and OUTx By default the clock on the OU...

Page 27: ...ocks are phase aligned A delay path t0 t4 associated with each of these dividers is available for applications that need a specific output skew configuration This is useful for PCB trace length mismatch compensation The resolution of the phase adjustment is approximately 0 28 ps per step definable in a range of 9 14 ns Phase adjustments are register configurable An example of generating two freque...

Page 28: ...e same result The SYNC pin provides another method of re aligning the R dividers without resetting the device This pin is positive edge triggered Asserting the sync register bit provides the same function R dividers can also be reset individually using the R divider reset bits 4 5 15 Output Crosspoint The output crosspoint allows any of the N dividers to connect to any of the clock outputs 4 5 16 ...

Page 29: ...peration of the Si5341 40 is controlled by reading and writing registers using the I2 C or SPI interface The I2C_SEL pin selects I2 C or SPI operation Communication with both 3 3V and 1 8V host is supported The SPI mode operates in either 4 wire or 3 wire See the Si5341 40 Family Reference Manual for details 4 9 Custom Factory Preprogrammed Parts For applications where a serial interface is not av...

Page 30: ...d settings 5 1 Addressing Scheme The device registers are accessible using a 16 bit address which consists of an 8 bit page address 8 bit register address By default the page address is set to 0x00 Changing to another page is accomplished by writing to the Set Page Address byte located at address 0x01 of each page 5 2 High Level Register Map Table 16 High Level Register Map 16 Bit Address Content ...

Page 31: ...th Divider N0 N4 Settings 0C MultiSynth Divider N0 Update Bit 17 MultiSynth Divider N1 Update Bit 22 MultiSynth Divider N2 Update Bit 2D MultiSynth Divider N3 Update Bit 38 MultiSynth Divider N4 Update Bit 39 58 FINC FDEC Settings N0 N4 59 62 Output Delay t Settings 63 94 Frequency Readback N0 N4 FE Device Ready Status 04 08 00 FF Reserved 09 01 Set Page Address 49 Input Settings 1C Zero Delay Mod...

Page 32: ...rnal reference clock REFCLK X2 10 7 I Notes 1 I Input O Output P Power 2 The IO_VDD_SEL control bit 0x0943 bit 0 selects 3 3 V or 1 8 V operation 3 The voltage on the VDDS pin s determines 3 3 V or 1 8 V operation GND Pad IN1 IN1 IN_SEL0 IN_SEL1 SYNC RST X1 XA XB X2 OE INTR VDDA IN2 IN2 SCLK A0 CS SDA SDIO A1 SDO VDD RSVD RSVD VDDO0 OUT0 OUT0 FDEC OUT1 OUT1 VDDO2 OUT2 OUT2 FINC LOL VDD OUT6 OUT6 V...

Page 33: ...ion and the pins left unconnected IN0 64 44 I IN1 1 1 I IN1 2 2 I IN2 14 10 I IN2 15 11 I FB_IN 61 41 I External Feedback Input These pins are used as the external feedback input FB_IN FB_IN for the optional zero delay mode See 4 5 13 Zero Delay Mode on page 28 for details on the optional zero delay mode FB_IN 62 42 I Table 17 Si5341 40 Pin Descriptions Continued Pin Name Pin Number Pin Type1 Func...

Page 34: ...rminations on page 26 Unused outputs should be left unconnected OUT0 23 19 O OUT1 28 25 O OUT1 27 24 O OUT2 31 31 O OUT2 30 30 O OUT3 35 36 O OUT3 34 35 O OUT4 38 O OUT4 37 O OUT5 42 O OUT5 41 O OUT6 45 O OUT6 44 O OUT7 51 O OUT7 50 O OUT8 54 O OUT8 53 O OUT9 59 O OUT9 58 O Table 17 Si5341 40 Pin Descriptions Continued Pin Name Pin Number Pin Type1 Function Notes 1 I Input O Output P Power 2 The I...

Page 35: ... as the A1 address input pin In 4 wire SPI mode this is the serial data output SDO pin See Note 2 SCLK 16 14 I Serial Clock Input This pin functions as the serial clock input for both I2C and SPI modes When in I2C mode this pin must be pulled up using an external resistor of at least 1 k No pull up resistor is needed when in SPI mode See Note 2 A0 CS 19 16 I Address Select 0 Chip Select This pin f...

Page 36: ... See Note 2 27 O Loss Of Lock This output pin indicates when the DSPLL is locked high or out of lock low It can be left unconnected when not in use See Note 3 LOS_XAXB 28 O Loss Of Signal This output pin indicates a loss of signal at the XA XB pins See note 2 SYNC 5 I Output Clock Synchronization An active low signal on this pin resets the output dividers for the purpose of re aligning the output ...

Page 37: ...EL 1 0 pins are used in the manual pin controlled mode to select the active clock input as shown in Table 14 See note 2 IN_SEL1 4 37 I RSVD 20 22 Reserved These pins are connected to the die Leave disconnected 21 55 56 NC 22 No Connect These pins are not connected to the die Leave disconnected Table 17 Si5341 40 Pin Descriptions Continued Pin Name Pin Number Pin Type1 Function Notes 1 I Input O Ou...

Page 38: ...ly Voltage 0 9 Supply voltage 3 3 V 2 5 V 1 8 V for OUTn OUTn outputs See the Si5341 40 Family Reference Manual for power supply fil tering recommendations Leave VDDO pins of unused output drivers unconnected An alternate option is to connect the VDDO pin to a power supply and disable the output driver to minimize current consumption VDDO1 26 23 P VDDO2 29 29 P VDDO3 33 34 P VDDO4 36 P VDDO5 40 P ...

Page 39: ...i5340 Si5340A A GM1 2 3 4 0 0001 to 800 MHz Integer 100 fs fractional 150 fs 44 Lead 7x7 QFN 40 to 85 C Si5340B A GM1 2 0 0001 to 350 MHz Si5340C A GM1 2 0 0001 to 800 MHz Integer Only 100 fs Si5340D A GM1 2 0 0001 to 350 MHz Si5341 40 EVB Si5341 EVB Evaluation Board Si5340 EVB Notes 1 Add an R at the end of the OPN to denote tape and reel ordering options 2 Custom factory pre programmed devices a...

Page 40: ...Dimension Min Nom Max A 0 80 0 85 0 90 A1 0 00 0 02 0 05 b 0 18 0 25 0 30 D 9 00 BSC D2 5 10 5 20 5 30 e 0 50 BSC E 9 00 BSC E2 5 10 5 20 5 30 L 0 30 0 40 0 50 aaa 0 10 bbb 0 10 ccc 0 08 ddd 0 10 Notes 1 All dimensions shown are in millimeters mm unless otherwise noted 2 Dimensioning and Tolerancing per ANSI Y14 5M 1994 3 This drawing conforms to the JEDEC Solid State Outline MO 220 4 Recommended ...

Page 41: ...Min Nom Max A 0 80 0 85 0 90 A1 0 00 0 02 0 05 b 0 18 0 25 0 30 D 7 00 BSC D2 5 10 5 20 5 30 e 0 50 BSC E 7 00 BSC E2 5 10 5 20 5 30 L 0 30 0 40 0 50 aaa 0 10 bbb 0 10 ccc 0 08 ddd 0 10 Notes 1 All dimensions shown are in millimeters mm unless otherwise noted 2 Dimensioning and Tolerancing per ANSI Y14 5M 1994 3 This drawing conforms to the JEDEC Solid State Outline MO 220 4 Recommended card reflo...

Page 42: ...reliminary Rev 0 9 9 PCB Land Pattern Figure 16 illustrates the PCB land pattern details for the devices Table 20 lists the values for the dimensions shown in the illustration Figure 16 PCB Land Pattern Si5341 Si5340 ...

Page 43: ... metal pads are to be non solder mask defined NSMD Clearance between the solder mask and the metal pad is to be 60 µm minimum all the way around the pad Stencil Design 5 A stainless steel laser cut and electro polished stencil with trapezoidal walls should be used to assure good solder paste release 6 The stencil thickness should be 0 125 mm 5 mils 7 The ratio of stencil aperture to land pad size ...

Page 44: ...e number Optional NVM code assigned for custom factory pre programmed devices Characters are not included for standard factory default configured devices See Ordering Guide for more information GM Package QFN and temperature range 40 to 85 C 3 YYWWTTTTTT YYWW Characters correspond to the year YY and work week WW of package assembly TTTTTT Manufacturing trace code 4 Circle w 1 6 mm 64 QFN or 1 4 mm...

Page 45: ...Si5341 40 Preliminary Rev 0 9 45 11 Device Errata Please log in or register at www silabs com to access the device errata document ...

Page 46: ...nd Si5340 data sheets Added application diagram Jun 2013 0 21 Minor updates from review cycle Added new SPI streaming command Added SPI timing diagrams Added high level register map July 2013 0 22 Minor edits July 2013 0 23 Changed FINC FDEC frequency step resolution from 0 05 ppb step to 0 01 ppb step Added REFCLK max input voltage swing specification of 1200 mVpp_se Si5341 pin changes Renamed pi...

Page 47: ... 30 Moved the register descriptions to the Si53451 40 Reference Manual Moved the majority of the contents of the Serial Interface section to the Si5341 40 Reference Manual Changed the output delay specification from 1 ps steps with a range of 8 32 ns to 0 28 ps steps with a range of 9 14 ns Added this to the specification table Updated LVCMOS output impedance values in Table 15 Added Control Input...

Page 48: ...tories assumes no responsibility for errors and omissions and disclaims responsibility for any consequences resulting from the use of information included herein Additionally Silicon Laboratories assumes no responsibility for the functioning of undescribed fea tures or parameters Silicon Laboratories reserves the right to make changes without further notice Silicon Laboratories makes no warran ty ...

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