Silicon Laboratories SI5324, Manual

Page: 5 / 61

Si5324
Preliminary Rev. 0.3 5
Output Clocks (CKOUT1, CKOUT2)
Common Mode V
OCM
LVPECL
100

load
line-to-line
V
DD
– 1.42 — V
DD
– 1.25 V
Differential Output Swing V
OD
1.1 — 1.9 V
Single Ended Output
Swing V
SE
0.5 — 0.93 V
Rise/Fall Time CKO
TRF
20–80%, f
OUT
= 622.08 MHz — 230 350 ps
Differential Duty Cycle
Uncertainty CKO
DC
LVPECL
100

load
line-to-line
Measured at 50% point
— — ±40 ps
PLL Performance (f
IN
= f
OUT
= 622.08 MHz, BW = 7 Hz)
Lock Time t
LOCK
End of ICAL to

of LOL
Loop Bandwidth = 7 Hz,
FAST_LOCK = 1,
LOCKT = 1
1 sec
Settle Time t
SETTLE
End of ICAL to 180° C of
final phase
60 sec
Phase Change After
Hitless Switch t
P-STEP
100 200 ps
Jitter Generation
LVPECL output format J
GEN
50 kHz–80 MHz — 320 420 fs rms
12 kHz–20 MHz — 290 410 fs rms
800 Hz–80 MHz — 320 450 fs rms
Jitter Peaking J
PK
— — 0.1 dB
Phase Noise CKO
PN
100 Hz offset — –95 — dBc/Hz
1 kHz offset — –110 — dBc/Hz
10 kHz offset — –117 — dBc/Hz
100 kHz offset — –118 — dBc/Hz
1 MHz offset — –131 — dBc/Hz
Spurious Noise SP
SPUR
Max spur @ n x F3
(n > 1, n x F3 < 100 MHz)
— –67 — dBc
Package
Thermal Resistance
Junction to Ambient

JA
Still Air — 32 — ºC/W
Thermal Resistance
Case to Ambient

JC
Still Air — 14 — ºC/W
Table 1. Performance Specifications (Continued)
(V
DD
= 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, T
A
= –40 to 85 ºC)
Parameter Symbol Test Condition Min Typ Max Unit
Notes:
1. For a more comprehensive listing of device specifications, please consult the Silicon Laboratories Any-Frequency
Precision Clock Family Reference Manual. This document can be downloaded from
www.silabs.com/timing .
2. This is the amount of leakage that the 3-level input can tolerate from an external driver. See the Family Reference
Manual. In most designs an external resistor voltage divider is recommended.