Rev. 0.1 1/12
Copyright © 2012 by Silicon Labs
Si53154-EVB
S i 5 3 1 5 4 - E V B
S i 5 3 1 5 4 E
V A L U A T I O N
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O A R D
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U I D E
Description
The Si53154 is a four port PCIe clock buffer compliant
to the PCIe Gen1, Gen2 and Gen3 standards. The
Si53154 is a 24-pin QFN device that operates on a
3.3 V power supply and can be controlled using SMBus
signals along with hardware control input pins. The
device is spread aware and accepts a frequency spread
differential clock frequency range from 100 to 210 MHz.
The connections are described in this document.
EVB Features
This document is intended to be used in conjunction
with the Si53154 device and data sheet for the following
tests:
PCIe Gen1, Gen2, Gen3 compliancy
Power consumption test
Jitter performance
Testing out I
2
C code for signal tuning
In-system validation where SMA connectors are
present
Si53154
SRC3
connection
for
application
SRC2
connection
for
application
SRC1
connection for
application
VDD = 3.3V
power supply
GND
SDATA
SCLK
SRC0
connection for
application
DIFF3 Output Enable
DIFF1 Output Enable
DIFF2 Output Enable
DIFF0 Output Enable
Power connectors
Differential
Clock Input
