Si53154-EVB
Rev. 0.1
5
Figure 4. Clock and Control Signals
Figure 5. Differential Clock Signals
SCLK/SDATA
DUTGND
DUTGND
DUTGND
DUTGND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
DUTGND
OE2
OE0
OE3
OE1
DUTGND
DUTGND
SSON
DUTGND
VDD
GND
VDD_3.3V
VDD_3.3V
VDD_3.3V
VDD_3.3V
VDD_3.3V
VDD_3.3V
VDD_3.3V
OE2
OE0
OE3
OE1
SSON
SCLK
SDATA
XIN_DIFFIN#
XOUT_DIFFIN
XOUT_DIFFIN1
SMA
R24
10K
P4
HEADER 1x3
1
2
3
P2
HEADER 1x3
1
2
3
R20
10K
R23
10K
XIN_DIFFIN#1
SMA
P1
HEADER 1x3
1
2
3
P3
HEADER 1x3
1
2
3
R17
10K
R15
10K
R16
10K
P6
HEADER 1x3
1
2
3
P5
HEADER 1x3
1
2
3
L1 SHOULD BE
SHORT AS POSSIBLE
L1 SHOULD BE
SHORT AS POSSIBLE
L1 SHOULD BE
SHORT AS POSSIBLE
L1 SHOULD BE
SHORT AS POSSIBLE
DUTGND
DUTGND
DUTGND
DUTGND
DUTGND
DUTGND
DUTGND
DUTGND
DUTGND
DUTGND
DUTGND
DUTGND
DUTGND
DIFF0
DIFF0#
DIFF1#
DIFF1
DIFF2#
DIFF2
DIFF3#
DIFF3
C28
2.0pF
DIFF0_1
SMA
C33
2.0pF
C30
2.0pF
C27
2.0pF
DIFF1_1
SMA
DIFF3#_1
SMA
DIFF2#_1
SMA
C32
2.0pF
C29
2.0pF
C34
2.0pF
DIFF3_1
SMA
DIFF1#_1
SMA
DIFF2_1
SMA
DIFF0#_1
SMA
C31
2.0pF
