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S i 5 2 1 4 7 - E V B

6

Rev. 0.1

Figure 4. Clock and Control Signals

Figure 5. Differential Clock Signals

SCLK/SDATA

DUTGND

DUTGND

DUTGND

DUTGND

DUTGND

DUTGND

DUTGND

DUTGND

DUTGND

DUTGND

DUTGND

DUTGND

DUTGND

DUTGND

DUTGND

VDD_3.3V

VDD_3.3V

VDD_3.3V

VDD_3.3V

VDD_3.3V

VDD_3.3V

VDD_3.3V

VDD_3.3V

VDD_3.3V

VDD_3.3V

VDD_3.3V

VDD_3.3V

VDD_3.3V

VDD_3.3V

SSON

NC_43

NC_44

OE0

OE1

SCLK

SDATA

XIN_DIFFIN#

XOUT_DIFFIN

OE2

OE3

OE4/5

OE6/8

NC_47

NC_48

CKPWRGD_PD#

P8

HEADER 1x3

1

2

3

P12

HEADER 1x3

1

2

3

R16

10K

P9

HEADER 1x3

1

2

3

R60

10K

P5

HEADER 1x3

1

2

3

P13

HEADER 1x3

1

2

3

R57

10K

R46

10K

R23

10K

R63

10K

XOUT_DIFFIN1

SMA

P4

HEADER 1x3

1

2

3

R38

10K

P1

HEADER 1x3

1

2

3

P2

HEADER 1x3

1

2

3

P10

HEADER 1x3

1

2

3

P7

HEADER 1x3

1

2

3

R48

10K

R20

10K

P11

HEADER 1x3

1

2

3

R15

10K

P6

HEADER 1x3

1

2

3

R24

10K

P3

HEADER 1x3

1

2

3

R36

10K

XIN_DIFFIN#1

SMA

R33

10K

R17
10K

L1 SHOULD BE
SHORT AS POSSIBLE

L1 SHOULD BE
SHORT AS POSSIBLE

L1 SHOULD BE
SHORT AS POSSIBLE

L1 SHOULD BE
SHORT AS POSSIBLE

DUTGND

DUTGND

DUTGND

DUTGND

DUTGND

DUTGND

DUTGND

DUTGND

DUTGND

DUTGND

DUTGND

DUTGND

DUTGND

L1 SHOULD BE
SHORT AS POSSIBLE

L1 SHOULD BE
SHORT AS POSSIBLE

DUTGND

DUTGND

DUTGND

DUTGND

DUTGND

DUTGND

DUTGND

L1 SHOULD BE
SHORT AS POSSIBLE

L1 SHOULD BE
SHORT AS POSSIBLE

DUTGND

DUTGND

L1 SHOULD BE
SHORT AS POSSIBLE

DUTGND

DUTGND

DUTGND

DUTGND

DUTGND

DUTGND

DUTGND

DUTGND

DIFF0_14

DIFF0#_15

DIFF1#_18

DIFF1_17

DIFF3#_22

DIFF3_21

DIFF4#_25

DIFF4_26

DIFF2#_20

DIFF2_19

DIFF5#_27

DIFF5_28

DIFF6#_30

DIFF6_31

DIFF7_33

DIFF7#_32

DIFF8_36

DIFF8#_35

C28
2.0pF

DIFF0

SMA

DIFF6

SMA

C57
2.0pF

C52
2.0pF

C33
2.0pF

DIFF8#_1

SMA

DIFF2

SMA

C30
2.0pF

C27
2.0pF

C54
2.0pF

C53
2.0pF

DIFF7#_1

SMA

DIFF1

SMA

C50
2.0pF

DIFF4#_1

SMA

C55
2.0pF

DIFF3#_1

SMA

C32
2.0pF

C51
2.0pF

DIFF5#_1

SMA

C29
2.0pF

DIFF8

SMA

DIFF6#_1

SMA

C34
2.0pF

DIFF2#_1

SMA

DIFF7

SMA

C58
2.0pF

DIFF4

SMA

DIFF1#_1

SMA

DIFF3

SMA

C56
2.0pF

C59
2.0pF

DIFF5

SMA

DIFF0#_1

SMA

C31
2.0pF

Summary of Contents for Si52147

Page 1: ... conjunction with the Si52147 device and data sheet for the following tests PCIe Gen1 Gen2 Gen3 compliancy Power consumption test Jitter performance Testing out I2 C code for signal tuning In system validation where SMA connectors are present Si52147 DIFF5 connection for application DIFF4 connection for application DIFF2 connection for application VDD 3 3 V power supply GND SDATA GND SCLK DIFF1 co...

Page 2: ...IFF6 DIFF7 DIFF8 enabled 0 DIFF6 DIFF7 DIFF8 disabled CLKPWGD PD I 3 3 V LVTTL Input After CLKPWGD active high assertion this pin becomes a real time input for asserting power down active low I2C connect For I2C read and write In sequence SData Gnd SCLK from left to right 3 3 V Power Supply VDD Connectors DIFF6 Differential output DIFF1 Differential output DIFF2 Differential output DIFF3 Different...

Page 3: ...n on the Output Internal 100 k pulldown 1 0 5 Spread enabled 0 Spread disabled SDATA I O SMBus Compatible SDATA SCLK I SMBus Compatible SCLOCK Table 2 Spread Selection SSON Frequency MHz Spread Note 0 100 00 OFF Default Value for SSON 0 1 100 00 0 5 Table 1 Input Jumper Settings Continued ...

Page 4: ...ential outputs with a saw tooth spread profile When the SSON is low spread profile is disabled 1 1 2 OE 0 8 Input The output enable pins can change on the fly when the device is on Deasserting valid low results in corresponding DIFF output to be stopped after their next transition with final state low low Asserting valid high results in corresponding output that was stopped are to resume normal op...

Page 5: ...1uF U1 Si52147 VDD_PCI 1 VDD_PLL3 2 OE0 3 OE1 4 SSON 5 VSS_PLL3 6 VSS_PLL4 7 OE2 8 OE3 9 OE4 5 10 OE6 8 11 VDD_PLL4 12 VDD_PLL2 13 SRC0 14 SRC0 15 VSS_PLL2 16 SRC1 17 SRC1 18 SRC2 19 SRC2 20 SRC3 21 SRC3 22 SRC4 25 SRC4 26 VSS_SRC 24 VDD_SRC 23 SRC5 27 SRC5 28 VSS_PLL1 29 SRC6 30 SRC6 31 SRC7 32 SRC7 33 VDD_PLL1 34 SRC8 35 SRC8 36 SCLK 37 SDATA 38 CKPWRGD_PDB 39 VDD_REF 40 XOUT 41 XIN CLKIN 42 NC_...

Page 6: ... L1 SHOULD BE SHORT AS POSSIBLE L1 SHOULD BE SHORT AS POSSIBLE L1 SHOULD BE SHORT AS POSSIBLE L1 SHOULD BE SHORT AS POSSIBLE DUTGND DUTGND DUTGND DUTGND DUTGND DUTGND DUTGND DUTGND DUTGND DUTGND DUTGND DUTGND DUTGND L1 SHOULD BE SHORT AS POSSIBLE L1 SHOULD BE SHORT AS POSSIBLE DUTGND DUTGND DUTGND DUTGND DUTGND DUTGND DUTGND L1 SHOULD BE SHORT AS POSSIBLE L1 SHOULD BE SHORT AS POSSIBLE DUTGND DUTG...

Page 7: ...Si52147 EVB Rev 0 1 7 NOTES ...

Page 8: ...th which if it fails can be reasonably expected to result in significant personal injury or death Silicon Laboratories products are generally not intended for military applications Silicon Laboratories products shall under no circumstances be used in weapons of mass destruction including but not limited to nuclear biological or chemical weapons or missiles capable of delivering such weapons Tradem...

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