S i 5 2 1 4 7 - E V B
6
Rev. 0.1
Figure 4. Clock and Control Signals
Figure 5. Differential Clock Signals
SCLK/SDATA
DUTGND
DUTGND
DUTGND
DUTGND
DUTGND
DUTGND
DUTGND
DUTGND
DUTGND
DUTGND
DUTGND
DUTGND
DUTGND
DUTGND
DUTGND
VDD_3.3V
VDD_3.3V
VDD_3.3V
VDD_3.3V
VDD_3.3V
VDD_3.3V
VDD_3.3V
VDD_3.3V
VDD_3.3V
VDD_3.3V
VDD_3.3V
VDD_3.3V
VDD_3.3V
VDD_3.3V
SSON
NC_43
NC_44
OE0
OE1
SCLK
SDATA
XIN_DIFFIN#
XOUT_DIFFIN
OE2
OE3
OE4/5
OE6/8
NC_47
NC_48
CKPWRGD_PD#
P8
HEADER 1x3
1
2
3
P12
HEADER 1x3
1
2
3
R16
10K
P9
HEADER 1x3
1
2
3
R60
10K
P5
HEADER 1x3
1
2
3
P13
HEADER 1x3
1
2
3
R57
10K
R46
10K
R23
10K
R63
10K
XOUT_DIFFIN1
SMA
P4
HEADER 1x3
1
2
3
R38
10K
P1
HEADER 1x3
1
2
3
P2
HEADER 1x3
1
2
3
P10
HEADER 1x3
1
2
3
P7
HEADER 1x3
1
2
3
R48
10K
R20
10K
P11
HEADER 1x3
1
2
3
R15
10K
P6
HEADER 1x3
1
2
3
R24
10K
P3
HEADER 1x3
1
2
3
R36
10K
XIN_DIFFIN#1
SMA
R33
10K
R17
10K
L1 SHOULD BE
SHORT AS POSSIBLE
L1 SHOULD BE
SHORT AS POSSIBLE
L1 SHOULD BE
SHORT AS POSSIBLE
L1 SHOULD BE
SHORT AS POSSIBLE
DUTGND
DUTGND
DUTGND
DUTGND
DUTGND
DUTGND
DUTGND
DUTGND
DUTGND
DUTGND
DUTGND
DUTGND
DUTGND
L1 SHOULD BE
SHORT AS POSSIBLE
L1 SHOULD BE
SHORT AS POSSIBLE
DUTGND
DUTGND
DUTGND
DUTGND
DUTGND
DUTGND
DUTGND
L1 SHOULD BE
SHORT AS POSSIBLE
L1 SHOULD BE
SHORT AS POSSIBLE
DUTGND
DUTGND
L1 SHOULD BE
SHORT AS POSSIBLE
DUTGND
DUTGND
DUTGND
DUTGND
DUTGND
DUTGND
DUTGND
DUTGND
DIFF0_14
DIFF0#_15
DIFF1#_18
DIFF1_17
DIFF3#_22
DIFF3_21
DIFF4#_25
DIFF4_26
DIFF2#_20
DIFF2_19
DIFF5#_27
DIFF5_28
DIFF6#_30
DIFF6_31
DIFF7_33
DIFF7#_32
DIFF8_36
DIFF8#_35
C28
2.0pF
DIFF0
SMA
DIFF6
SMA
C57
2.0pF
C52
2.0pF
C33
2.0pF
DIFF8#_1
SMA
DIFF2
SMA
C30
2.0pF
C27
2.0pF
C54
2.0pF
C53
2.0pF
DIFF7#_1
SMA
DIFF1
SMA
C50
2.0pF
DIFF4#_1
SMA
C55
2.0pF
DIFF3#_1
SMA
C32
2.0pF
C51
2.0pF
DIFF5#_1
SMA
C29
2.0pF
DIFF8
SMA
DIFF6#_1
SMA
C34
2.0pF
DIFF2#_1
SMA
DIFF7
SMA
C58
2.0pF
DIFF4
SMA
DIFF1#_1
SMA
DIFF3
SMA
C56
2.0pF
C59
2.0pF
DIFF5
SMA
DIFF0#_1
SMA
C31
2.0pF