S i 5 2 1 4 7 - E V B
2
Rev. 0.1
1. Front Panel
Figure 1. Evaluation Module Front Panel
Table 1. Input Jumper Settings
Jumper Label
Type
Description
OE0
I
OE0, 3.3 V Input for Enabling DIFF0 Clock Output
.
1 = DIFF0 enabled, 0 = DIFF0 disabled.
OE1
I
OE1, 3.3 V Input for Enabling DIFF1 Clock Output
.
1 = DIFF1 enabled, 0 = DIFF1 disabled.
OE2
I
OE2, 3.3 V Input for Enabling DIFF2 Clock Output
.
1 = DIFF2 enabled, 0 = DIFF2 disabled.
OE3
I
OE3, 3.3 V Input for Enabling DIFF3 Clock Output
.
1 = DIFF3 enabled, 0 = DIFF3 disabled.
OE4/5
I
OE4/5, 3.3 V Input for Enabling DIFF4 and DIFF5 Clock Outputs.
1 = DIFF4 & DIFF5 enabled, 0 = DIFF4 & DIFF5 disabled.
OE6/8
I
OE6/8, 3.3 V Input for Enabling DIFF6, DIFF7 and DIFF8 Clock Outputs.
1 = DIFF6, DIFF7 & DIFF8 enabled, 0 = DIFF6, DIFF7 & DIFF8 disabled.
CLKPWGD/PD
I
3.3 V LVTTL Input.
After CLKPWGD (active high) assertion, this pin becomes a real-time input for
asserting power down (active low).
I2C connect -For I2C read and
write. In sequence SData, Gnd,
SCLK from left to right
.
3.3 V Power Supply
VDD Connectors
DIFF6 Differential output
DIFF1 Differential output
DIFF2 Differential output
DIFF3 Differential output
DIFF0 Differential output
External Clock Input for
on Si52147-EVB only
SSON, OE2, OE3, OE4/5 and
OE6/8 hardware inputs
control for Spread enable,
DIFF2, DIFF3, DIFF4 though
DIFF5 and DIFF6 through
DIFF8 outputs respectively
Si52147 device mount
GND Connector
OE0 and OE1 hardware input
control for DIFF0 and DIFF1
outputs respectively
DIFF4 Differential output
DIFF5 Differential output
DIFF7 Differential output
DIFF8 Differential output
CKPWRGD/ Power down input
control
