Rev. 0.1 1/12
Copyright © 2012 by Silicon Labs
Si52147-EVB
S i 5 2 1 4 7 - E V B
S i 5 2 1 4 7 E
V A L U A T I O N
B
O A R D
U
S E R
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S
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U I D E
Description
The Si52147 is a nine port PCIe clock generator
compliant to the PCIe Gen1, Gen2 and Gen3 standards.
The Si52147 is a 48-pin QFN device that operates on a
3.3 V power supply and can be controlled using SMBus
signals along with hardware control input pins.The
differential outputs support spread spectrum and can be
controlled through SSON input pin. The Si52147 needs
a crystal or clock input of 25 MHz. The connections are
described in this document.
EVB Features
This document is intended to be used in conjunction
with the Si52147 device and data sheet for the following
tests:
PCIe Gen1, Gen2, Gen3 compliancy
Power consumption test
Jitter performance
Testing out I
2
C code for signal tuning
In-system validation where SMA connectors are
present
Si52147
DIFF5
connection
for
application
DIFF4
connection
for
application
DIFF2 connection
for application
VDD = 3.3 V
power supply
GND
SDATA
GND
SCLK
DIFF1 connection for
application
Spread Enable Control
DIFF2 Output Enable
DIFF4/DIFF5 Output Enable
DIFF6/DIFF8 Output Enable
Power connectors
External
Clock Input
DIFF3 connection
for application
DIFF6
connection
for
application
DIFF7 connection
for application
DIFF8 connection
for application
DIFF3 Output Enable
DIFF1 Output Enable
DIFF0 Output Enable
DIFF0 connection
for application
CKPWRGD/Power down enable
SDATA/SCLK
