Silicon Graphics CHALLENGE L, User Manual, Page: 156 / 164

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Appendix E: Challenge VMEbus Implementation
Table E-4 Signal Definitions
Signal Name Definition
D00 through
D31 Data lines. These lines are tri-state and are not defined until the
data strobes (DS0* and DS1*) are asserted by the MASTER.
A00 through
A31 Address lines. These lines are tri-state and are not defined until
the address strobe (AS*) is asserted by the MASTER.
AM0 through
AM5 Address modifier lines. Asserted by the MASTER and indicates
the type of data transfer to take place. VME SLAVEs look at the
lines to determine if they will respond and what type of response
to make.
DS0, DS1 Data Strobe lines. Asserted by the MASTER and indicates stable
data on the data bus.
AS Address strobe. Is asserted by the MASTER and indicates a stable
address is present on the address lines.
BR0 through
BR3 Bus request lines. The MASTER requests a busy bus via these
prioritized levels.
BG0IN through
BG3IN Bus grant in (daisy-chained).
BG0OUT
through
BG3OUT Bus grant out (daisy-chained).
BBSY Busy.
BCLR Bus clear. (Hint to bus master, VME MASTERs are not required
to comply.)
IRQ1 - IRQ7 Interrupt request lines.
IACK Interrupt acknowledge. Asserted by MASTER to indicate the
VME interrupt level to be serviced.
IACKIN Interrupt acknowledge in (daisy-chained).
IACKOUT Interrupt acknowledge in (daisy-chained).