Silicon Graphics CHALLENGE L, User Manual, Page: 152 / 164

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Appendix E: Challenge VMEbus Implementation
Note that in some VME enclosures, these plates supply the required
additional EMI shielding. However, the Challenge chassis already provides
sufficient shielding for boards inside the chassis, so these plates are not
necessary.
VME Pins
Table E-1 through Table E-3 list the pin assignments of the VME P1, P2, and
P3 connectors. Table E-4 describes the pin signals.
Note:
No connections are made to rows A and C of connector P2. These lines
are not bused across the backplane. The P3 connector uses the SUN power
convention. In addition, the Challenge system does not generate ACFAIL* or
SYSFAIL*. The SERCLK and SERDAT* are also unused.
The Challenge system supplies the defined voltages to the bus and also
asserts SYSREST* and drives SYSCLK (SYSCLK is driven at 16 MHz).
On Challenge system backplanes, the unused VME pins on P1/P2/P3 are no
connects .
Table E-1 P1 VME Pin Assignments
Pin Row A Row B Row C
1 D00 BBSY* D08
2 D01 BCLR* D09
3 D02 ACFAIL D10
4 D03 BG01N* D11
5 D04 BG0OUT* D12
6 D05 BG1IN* D13
7 D06 BG1OUT* D14
8 D07 BG2IN* D15
9 GND BG2OUT* GND
10 SYSCLK BG3IN* SYSFAIL*