SC5313A Operating & Programming Manual
Rev 1.0.2
30
the device will need to be reset externally. The time required to process a command is also dependent
on the command itself; measured times for command completions are typically between
to
after reception. The user may choose to wait a minimum of
or query the SERIAL_READY
bit before sending in another command; the latter is recommended for robustness. The minimum wait
time between successive polls of the SERIAL_READY register is
.
Figure 4: SPI Mode - Data clocked in on falling clock edge.
Figure 5. SPI timing.
Additional SPI Registers
There are two additional registers available for SPI communication as shown in Table 8. Data byte(s)
associated with registers can be “zeros” or “one”; it doesn’t matter which value since the device ignores
them. They are only required for clocking out the returned data from the device.
Table 8. Additional SPI registers.
Register Name
Register
Address
Serial
Range
Bit 7
(MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSB)
SERIAL_READY
0x04
[7:0]
SPI_OUT_BUFFER
0x22
[7:0]
Open
[15:8]
Open
[23:16]
Open
[31:24]
Open
MSB
CS
MISO
MOSI
CLK
MSB
LSB
LSB
T
S
T
B
T
C
8 Bit Command/ Reg. Address
Upper 8 Control/Data
Lower 8 Control/Data
T
S
: Time between CS assertion and first clock cycle >= 5 uS
T
C
: Clock period = 1 uS typical (Clock rate depends on signal integrity from host)
T
B
: Duration between byte transfer >= 10 uS
CLK
DATA
CS
ALTERNATE
CS
