
Contents
S7-300 Programmable Controller Hardware and Installation
A5E00105492-01
ix
7-1
Integrated I/O of CPU 312 IFM .........................................................................7-6
7-2
Integrated I/O of CPU 314 IFM .........................................................................7-7
7-3
Integrated I/O of CPU 312C ..............................................................................7-7
7-4
Integrated I/O of CPU 313C ..............................................................................7-8
7-5
Integrated I/O of CPU 313C-2 PtP/DP..............................................................7-8
7-6
Integrated I/O of CPU 314C-2 PtP/DP..............................................................7-9
8-1
Recommended commissioning procedure - Part I: Hardware ..........................8-2
8-2
Recommended commissioning procedure - Part II: Software ..........................8-3
8-3
Possible causes of a CPU request to reset memory ......................................8-14
8-4
Procedure for CPU memory reset...................................................................8-15
8-5
Internal CPU events on memory reset ............................................................8-17
8-6
Software requirements ....................................................................................8-24
8-7
DP address areas of the CPUs .......................................................................8-25
8-8
Event recognition by CPUs 31x-2 DP/31xC-2 DP operating as DP master ...8-27
8-9
Event recognition by CPUs 31x-2 DP/31xC-2 DP as DP slave ......................8-30
8-10
Configuration example for the address areas in intermediate memory ..........8-32
9-1
Backup of the operating system on MC or MMC ..............................................9-2
9-2
Operating system update with MC/MMC ..........................................................9-4
10-1
Differences between Forcing and Controlling of Variables.............................10-3
10-2
Status and error displays ................................................................................10-8
10-3
Evaluation of the SF LED (Software error) .....................................................10-9
10-4
Evaluation of the SF LED (Hardware error) ..................................................10-10
10-5
The BUSF, BUSF1 and BUSF2 LEDs ..........................................................10-11
10-6
BUSF LED is lit..............................................................................................10-11
10-7
BUSF LED flashes ........................................................................................10-11
10-8
Event recognition of CPU 31x-2 operating as DP master.............................10-13
10-9
Evaluating RUN to STOP transitions of the DP slave in the DP master.......10-14
10-10
Reading out diagnostic data in the master system, using STEP 5
and STEP 7 ...................................................................................................10-16
10-11
Event recognition of CPUs 31x-2 operating as DP slave .............................10-20
10-12
Evaluating RUN-STOP transitions in the DP Master/DP Slave ....................10-20
10-13
Structure of station status 1 (Byte 0).............................................................10-23
10-14
Structure of Station Status 2 (Byte 1) ...........................................................10-23
10-15
Structure of Station Status 3 (Byte 2) ...........................................................10-24
10-16
Structure of the Master PROFIBUS address (byte 3) ...................................10-24
10-17
Structure of the manufacturer ID (byte 4 and 5) ...........................................10-24
11-1
Startup of the system after specific events .....................................................11-1
11-2
Mains voltage ..................................................................................................11-2
11-3
Protection against external electrical interference ..........................................11-2
11-4
Protection against external electrical interference ..........................................11-2
11-5
Coupling mechanisms.....................................................................................11-5
11-6
Keys for sample 1 .........................................................................................11-10
11-7
Cable routing inside buildings .......................................................................11-15
11-8
High-voltage protection of cables with the help of surge protection
equipment......................................................................................................11-22
11-9
Low-voltage protection for lightning protection zones 1 <-> 2 ......................11-24
11-10
Low-voltage protection for lightning protection zones 2 <-> 3 ......................11-25
11-11
Example of a circuit conforming to lightning protection requirements
(legend to previous figure) ............................................................................11-27
Summary of Contents for Simatic S7-300
Page 10: ...Contents S7 300 Programmable Controller Hardware and Installation x A5E00105492 01 ...
Page 16: ...Preface S7 300 Programmable Controller Hardware and Installation 1 6 A5E00105492 01 ...
Page 22: ...Quick Guide S7 300 Programmable Controller Hardware and Installation 2 6 A5E00105492 01 ...
Page 28: ...Product overview S7 300 Programmable Controller Hardware and Installation 3 6 A5E00105492 01 ...
Page 74: ...Configuring S7 300 Programmable Controller Hardware and Installation 4 46 A5E00105492 01 ...
Page 102: ...Wiring S7 300 Programmable Controller Hardware and Installation 6 18 A5E00105492 01 ...
Page 148: ...Commissioning S7 300 Programmable Controller Hardware and Installation 8 36 A5E00105492 01 ...
Page 236: ...Glossary S7 300 Programmable Controller Hardware and Installation 12 16 A5E00105492 01 ...