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TD_Repair_L2.5_A70_A75_R1.0.pdf Release
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The Bit Manipulation Unit consists of a full 36-bit barrel shifter, an exponent unit, a bit-field
operation unit, two 36-bit accumulator registers B0 and B1, and a shift value register.
The Data Address Arithmetic Unit performs all the address storage and address calculation
necessary for accessing the data and program memories. It also supports a software stack
pointer, loop counter, and min/max operations.
The key features of TEAKlite core are as follows:
• 16-bit fixed-point DSP core
• 16 x 16-bit 2’s complement parallel multiplier with a 32-bit product
• Single cycle multiply-accumulate instructions
• 36-bit ALU
• 36-bit left/right barrel shifter
• Four 36-bit accumulators
• Software stack residing in the data RAM
• User-defined registers off-core
• Three high-active interrupt input lines INT0, INT1, and INT2
• Automatic context switching by interrupts
• Up to 16-bit Bit Field Operations (BFO)
• Three modes for power saving features: Operational, Idle, and Sleep.
• The maximum Frequency is 104 MHz. The TEAKlite core clock is scalable to lower
frequencies.
In the DSP Firmware are implemented the following functions:
The High Speed Circuit Switched Data (HSCSD) class 4 is supported.
The packet-oriented data (GPRS) class 4 is supported with a coding schemes from 1 to 4. It
provides fixed, dynamic and extended dynamic modes.
If the E-GOLDlite is used as a modem, the HSCSD and GPRS class 10 is supported. The
packet-oriented data (GPRS) class 10 is supported with a coding schemes from 1 to 4. It
provides fixed, dynamic, and extended dynamic modes.
Synchronisation and Measurements
• Scanning of channels (measurement of the field strengths of neighboring base
stations)
• Detection and evaluation of Frequency Correction Bursts.
Equalization
There is equalization of GMSK Normal Bursts and Synchronization Bursts with bit-by-bit
soft output.
Channel Coder/Decoder
There are Channel Coders/Decoders for 2.4kbits/s, 4.8kbits/s, 9.6kbits/s, and 14.4kbits/s.