Company Confidential
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Com
Copyright 2005© Siemens AG
Page
37
of
53
TD_Repair_L2.5_A70_A75_R1.0.pdf Release
1.0
Power Supply Functions:
Functions Pin
Requirements
Implementation/Sequence
Switching on the
mobile phone
ON_OFF,
ON_OFF2,
VDD_CHARGE
There are 3 different possibilities to switch on the phone by
external pins:
-
VDD_CHARGE with rising edge after POR or high level at
end of POR signal
-
ON/OFF with falling edge
-
ON/OFF2 with rising edge
In order to guarantee a defined start-up behaviour of the
external components, a sequential power up is used and the
correct start up of these blocks is supervised. In active mode,
a continuous signal at watchdog is needed to keep the
system running. If the signals fails, the ASIC will switch to
power down mode. It must be guaranteed that each start-up
condition does not interfere and block the other possible
startup signals. In case of failure during start-up, the device
will go back to power down mode. To guarantee that
VDDCHARGE is always sensed we must be able to detect
whether the VDDCHARGE will have a rising edge during
POR (this can happen in case of an empty battery). Therefore
this signal is sensed as level sensitive at the end of POR and
edge sensitive after POR signal.
Watchdog
monitoring
WDOG
As soon as the first WDOG pin rising is detected during the
TE4 timer, the device start the watchdog monitoring
procedure. Standard switch off of the phone is the watchdog.
The first edge of watchdog is rising. If a falling edge is
detected as the first transient the device will go to power
down mode again and the whole phone is switched off. Rising
and falling edges must be detected alternated. With any edge
on WDOG pin a counter will be loaded. The next - compared
to the previous edge - inverted edge must occur between end
of T1, and end of T2. If the signal occurs before end of T1 or
is not detected until end of T2, the device will go to power
down mode immediately after the violation of the watchdog
criteria occurs.
T1 min. 0,327s/ typ. 0,360s/ max. 0,400s
T2 min. 2,600s/ typ. 2,860s/ max. 3,178s
Power-On-Reset
(POR)
RESET_N
RESET2_N
To guarantee a correct start-up of the ASIC, a power on reset
is needed at first power supply ramping. Therefore a
static/dynamic power on reset circuit is added, which creates
a reset each time the power supply is connected. After POR
the ASIC starts up the reference and the oscillator, read in the
fuse content and goes back to power down mode. If the
power supply will drop under the POR threshold V
th,POR_L
a
synchronous reset is done and the ASIC will go to power
down mode independently of the previous operating mode.
V
th,POR_L
= min. 2.38/ typ. 2.43/ max. 2.48V
Voltage Supply
Logics
REG1
(2.65V)
The linear controller is designed for 2.65V(
±
2%) and a
maximum load current of 140 mA.
Voltage and current for the external Logic is supplied from the
internal 2.65V logic regulator. The operating voltage VREG1
is kept constant up to the maximum rated load current. A
reference voltage for the regulator circuit is generated from a
bandgap reference
