Shuttle HOT-433 User Manual Download Page 1

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Summary of Contents for HOT-433

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Page 3: ... document nor does it make a commitmellf lo update the information coutained herein TRADEMARKS UAt C is a registered trademark of l J Iited Microelectronics Corporation PC AT is a registered trademark of lllfemational Business Machine Corporation OS 2 is a registered trademark of IBM Corporation NetWare is a registered trademark of NoveJJ Corporation All Olher brand and product names refered 10 in...

Page 4: ...5 Power Management Modes Indicator 26 EPMI Connector GR S JP35 26 Power Supply PowerDownConnector JP6 26 CHAPTER 6 BIOS SETUP 27 BIOS SetupFeature Using theKeyboard withWinBIOS Setup Standard Setup Advanced Setup Advanced SetupDefaults Chipset Setup Chipset Setup Defaults Power Management Setup Power Management SetupDefaults Peripheral Setup Peripheral SetupDefaults WinBIOS Password Support 28 30 ...

Page 5: ...ry cache memory architecture from 1 28KB up to 1024KB HOT 433 mainboard features four PCI Pherpherial Component Interconnect local bus and four ISA Industry Standard Architec ture bus expansion slots HOT 433 mainboard also integrate one 2 channel PCI enhanced IDE controller one floppy controller one parallel port two serial ports and one optional PS 2 mouse port User sManual3 ...

Page 6: ...rite back cache 0 Supports PC master and slave up to 33MHz 0 Supports PC burst mode access to local memory Memory 0 Supports four banks of local DRAM system ranging from I MB to 256MB of host memory 0 Supports 256K x 36 32 1 MB 5 12K x 36 32 2MB 1 M X 36 32 4MB 2M X 36 32 8MB 4 M X 36 32 1 6MB 8M x 36 32 32MB and 1 6M x 36 32 64MB 72 pins SIMM Cache Memory 0 Supports 128KB 256KB 5 12KB and 1 MB wr...

Page 7: ...up to 4 IDE drives Supports 32 and 1 6 bit data transfers Supports buffers that operate read prefresh and write port transactions Fully ANSI ATA spec 3 X compatible 0 One floppy port 0 One parallel port Supports SPP Standard Parallel Port EPP Enhanced Parallel Port and ECP Extended Capabilities Port high performance parallel modes 0 Two serial ports Supports 1 6C550 compatible UARTS 0 One PS 2 mou...

Page 8: ...m I Bnw 1 I DRAM I PCI Bus r ISA PCI Floppy IDE 1 j I T I ISA Parallel Serial ISA Bus Keyboard 6 User s Manual CPU UM8881 F UM8886AF 8002 BIOS I L2 CacheI PCI Bus Master Slots D _ ISA Bus Slots XD Bus CMOS and RTC ...

Page 9: ...er a local DRAM controller and an integrated Periph erals controller 6 12 II D 2 System Microprocessor 433 mainboard accept any member of the 486 family of high perfor mance 32 bit microprocessors in PGA package The mainboard is designed to run at a clock speed from 25 to 50MHz on CPU bus clock and 25 to 1 OOMHz on CPU core clock 3 External Cache 433 maniboard features a external cache memory whic...

Page 10: ...enormous flex ibility in designing custom platforms 7 5V 3 3 3 45 3 6 4 0V Voltage Selection For Intel 486DX4 P24C AMD Am486DX2 80 DX4 J 00 and Cyrix 486DX2 66 DX2 80 CPU 433 mainbaord provides a wide selection of voltages support of 3 3 3 45 3 6 4 0V 8 On board PCI IDE Controller 433 mainboard provides a on board 2 channel IDE controller with high speed data transfer rate It support up to four ID...

Page 11: ... offer optimum performance ofthe mainboard 13 Attached Accessories one 40 pin hard disk drive flat cable one 34 pin floppy disk drive flat cable one 9 pin and 25 pin serial connectors with cables one 25 pin parallel port connector with cable optional PS 2 5 pin DIN connector with cable on board enhanced IDE drivers on a 3 5 floppy diskette User s Manual 9 ...

Page 12: ...433 Mainboard Placement c r 0 2System BIOS I 1 v 1 10 lJl 51JPJ6 JP 7 JP20 m 0 m J 1L 111 CIIIDCIIIDCIXIUIIID mP SOCKET 3 Memory Bank 3 2 I 0 II nnn Cache Bank 0 uuu D Cache Bank I D 10 User s Manual ...

Page 13: ...er jumper settings for generating 25MHz to 50MHz clock frequency for 486 system are shown bellow 25MHzSystem Clok 1 1 11 1 JPl 1 I I IIJP2 11 I IJPJ 140MHzSystem Clok 11 1 11 1 JPI 1 II I IJP2 11 I IJPJ JPI I I 6 v JP2 1 1 JP3 I I 6 External Keyboard BIOS SA Slot I SA Slot 2 SA Slot 3 33MHzSystem C ok 11 1 1 1 JPl 1 JP2 11 I IJPJ 50MHz System Clok I 11 1 1 1 JPI 1 I I IIJP2 1 11 11JP3 User s Manua...

Page 14: ...JP26 I JP28 I JP30 1TI I II I II TI J JI J I JP25 I JP27 I JP29 JP31 JP32 Intel 486DXIDX2 1 JP 1 7 2 6 1 JP20 ooooooooooooooooooo ooooooooooooooooooo ooooooooooooooooooo ooooooooooooooooooo 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 00000 0000 ooooooooooooooooooo oooooooooooooooooo 000000000000000000 0 0000000000000000 1 L3 JOS i N r l ll 1r 1 1 a il ...

Page 15: ...P26 I JP28 I JP30 fii JI II I 1 11 w I IT I JP25 I JP27 I JP29 JP31 JP32 Intel 486SX S Series 1JPl7 2 6 l JP20 11 1 Jrer rel t l l ll llfil l l 11 ll J 1 JP19 5 1 JP21 JP23 N V ti 1 JP26 I JP28 1 JP30 0 I il l l H I lr 11 I I IT I JP25 1 JP27 1 JP29 JP31 JP32 User s Manual 1 3 ...

Page 16: ...Intel 486DX4 P24C AMD Enhanced Am486 Clock Multiplier JP18 For 3 3 V Intel 486DX4 P24C and AMD Enhanced Am486 CPU 433 mainboard offers a jumper JP1 8 to adjust CPU internal clock multiplier to 2 or 3 t imes of external clock frequency Core Bus CPU Type Clock JPIS Ratio DX4 100 3 1 1 1 DX4 l 00 2 1 I DX4 75 3 1 1 1 Other CPU 1 1 1 4 User s Manual Internal External Core Clock Bus Clock lOOMHz 33MHz ...

Page 17: ...1 1 1 II 1 1 I i liiiiiilll 1 1 _ _ JI 11 J I JP25 1 JP27 I JP29 JP31 JP32 tv Intel P24D Internal Cache Line JP24 Intel P24D CPU Cache Cache Scheme Write Back Write Thru Other CPU Intel P24T I JP 17 2 6 l JP20 Line JP24 1 1 11 1 1 1 1 l ii I C IIJIIJil lfil g ll ll Jtv 1 JP19 5 1 JP21 JP23 l 0 User s Manual 1 5 J ...

Page 18: ...6DX4 100 DX2 80 Clock Multiplier JP24 For AMD 3 3V Am486DX4 I 00 and Am486DX 80 CPU 433 mainboard offers a jumper JP 4 to adjust CPU internal clock multiplier to 2 or 3 times of external clock frequency I JP24 f 1 1 p AMD 48 6DX2 80 DX4 100 Clock Multiplier CPU Type External Ratio Bus Clock DX4 IOO 3 I 33MHz DX4 IOO 2 I IOOMHz SOMHz DX2 80 3 I 75MHz 25MHz DX2 80 2 I 80MHz 40MHz Other CPU 16 User s...

Page 19: ...P17 2 6 1 JP20 r ml ll li j 11 1 11 l II IL J L I JP I9 5 1 JP21 JP23 Y l 1 JP26 I JP28 1 JP30 m J I l i llr l i II IJc 1 1 I I iii II II I 1 JP25 1 JP27 I JP29 JP31 JP32 Cyrix Cx486DX4 100 1 JP17 2 6 1 JP20 lli il Jc I II li illi ill1 1 g 4t 1 l ll l tv l il ii 1 JP195 1 JP21 JP23 18 l l Vl l IP21 1 JP26 1 JP28 1 JP30 0 I ellli il liiiiiiil II liiiiiiil I I lii ii IHI iiiil II I 1 JP25 1 JP27 1 J...

Page 20: ...C 486S U5 1 JP17 2 6 1 JP20 r 1_ l 1 JP19 5 I JP21 JP23 v t o 1 JP26 I JP28 l JP30 0 I1 1 11 l iiiiil lll iiiiill iiiiil I l i i lII l iiiiil l iiiiilICITJ I JP25 I JP27 I JP29 JP31 JP32 18 User s Manual ...

Page 21: ...rovided for voltage setting between 5V and 3 3 3 45 3 6 4 0 3 3V UJ 3 45V ee 3 6V ee 4 0V ee 0 1 JPIS 1 1 1 JP16 1 1 CPU Voltage Selection CPU Voltage JPIS JPI6 5V 1 1 11 1 1 3 3 v 3 45 v 3 6V iu I il i 4 0V 0000000000000000000 0000000000000000000 0000000000000000000 0000000000000000000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 00000 0000 JP9 Don t C...

Page 22: ...rd is 32Kx8 64Kx8 and 1 28Kx8 the Tag SRAM can be 8Kx8 3 2Kx8 and 64Kx8 1128KB Cache Memory Cache BankO Bank1 Data RAM Data RAM Size U15 16 17 18 U27 28 29 30 128KB 32 Kx8 Empty 1256KB Cache Memory Cache BankO Bank1 Data RAM Data RAM Size U15 16 17 18 U27 28 29 30 256KB 32Kx8 32Kx8 20 User s Manual I I I I 2 i 0 0 Tag RAM Cacheable Range U26 Write Through 1 Write Back 8Kx8 32MB I 16MB I I I I 2 I ...

Page 23: ...7 18 U27 28 29 30 512KB 64Kx8 64Kx8 I1024KB Cache Memory Cache BankO Bank1 Data RAM Data RAM Size U15 16 17 18 U27 28 29 30 1024 KB 128K x 8 128Kx8 Tag RAM U26 32Kx8 Tag RAM U26 32Kx8 Tag RAM U26 32Kx8 Tag RAM U26 64Kx8 Cacheable Range Write Through I Write Back 64 MB I 32MB I 2 I C o 0 _ Cacheable Range Write Through 1 Write Back 128MB I 64MB I 2 I _ Cacheable Range Write Through I Write Back 128...

Page 24: ...5 On board Floppy Controller Connector CN4 On board Parallel Port Connector CN3 On board Serial port I Connector CN2 On board Serial Port 2 Connector CNI External Battery Connector CN9 Power LED and Keylock Connector CN8 PC Speaker Connector MS I PS 2 Mouse Connector JP33 RESET Hardware Reset Switch Connector JP34 TB S Hardware Turbo Switch Connector LEDI TB L Turbo LED connector Power Management ...

Page 25: ...ation of 433 mainboard 433 Memory Configuration Reference Table BANK 0 BANK 1 BANK 2 BANK 3 TOTAL 1MB NONE NONE NONE 1MB 1MB 1MB NONE NONE 2MB 1MB 1MB 1MB NONE 3MB 1MB 1MB 1MB 1MB 4MB 2MB NONE NONE NONE 2MB 2MB 2MB NONE NONE 4MB 2MB 2MB 2MB NONE 6MB 2MB 2MB 2MB 2MB 8MB 4MB NONE NONE NONE 4MB 4MB 4MB NONE NONE 8MB 4MB 4MB 4MB NONE 12MB 4MB 4MB 4MB 4MB 16MB 8MB NONE NONE NONE 8MB 8MB 8MB NONE NONE 1...

Page 26: ... 64MB NONE 192MB 64MB 64MB 64MB 64MB 256MB 1MB 1MB 2MB 2MB 6MB 1MB 1MB 4MB 4MB lOMB 1MB 1MB 8MB 8MB 18MB 1MB 1MB 16MB 16MB 34MB 1MB 1MB 32MB 32MB 66MB 2MB 2MB 4MB 4MB 12MB 2MB 2MB 8MB 8MB 20MB 2MB 2MB 16MB 16MB 36MB 2MB 2MB 32MB 32MB 68MB 4MB 4MB 8MB 8MB 24MB 4MB 4MB 16MB 16MB 40MB 4MB 4MB 32MB 32MB 72MB 8MB 8MB 16MB 16MB 48MB 8MB 8MB 32MB 32MB 80MB 16MB 16MB 32MB 32MB 96MB 16MB 16MB 64MB 64MB 160...

Page 27: ...oppy PCI master ISA master DMA one programmable memory region and one programable 110 region DOZE mode In this mode CPU frequency is reduce to l 2 of 10rmal frequency and the SLEEP timer 2 min to 5 1 2 min starts counting when there is no activity When the timer expire the system will enter into SLEEP mode The activities monitored are the same as in ON mode SLEEP mode In this mode CPU frequency is...

Page 28: ...terrupt pin is provided for special platform which offer a sleep suspend resume but ton Pushing the button will force 433 mainboard to go into SLEEP or SUSPEND mode depending on the type ofthe CPU The mainboard will restart when the button is push again Power Supply Power Down Connector JP6 433 mainboard also provides a power supply power down con nector to control the external A C output on the s...

Page 29: ...u want to run SETUP Press Del to run WinBIOS Setup Mouse Supports in WinBIOS Setup The following types of mouse devices are supported PS 2 type mouse Bus mouse that use IRQs 3 4 or 5 IRQ2 is not supported Microsoft compatible mouse Logitech C series compatible mouse using the MM protocol WinBIOS Setup can be accessed via keyboard mouse or pen The mouse click functions are single click to change or...

Page 30: ...h section contains several icons Clicking on each icon acti vates a specific function The WinBIOS Setup icons and func tions are described in this chapter The sections are Setup This section has five icons that permit you to set system configu ration options such as date time hard disk type floppy type chipset parameter power management and peripherall 0 setup Utilities This section has two icons ...

Page 31: ...e WinBIOS Setup main menu The types of default are Original Optimal Fail Safe This option restore the original setting that was recorded in the CMOS RAM This option will set the mainboard with the best performance parameters This option set the mainboard with m inimum startup parameters If you cannot boot the com puter successfully select the Fail Safe WinBIOS Setup options and try to diagnosethe ...

Page 32: ... Increments a value Decrements a value Esc Closes the current operation and return to previous level PgUp Returns to the previous page PgDn Advances to the next page Home Returns to the beginning of the text End Advances to the end of the text Alt H Access a help window Alt Spacebar Exit WinBIOS Setup Alphabetic keys A to Z are used in the Virtual Keyboard and are not casesensitive Numeric Keys 0t...

Page 33: ...1 KB CJ 1 44 MB CJ 2 88 MB 1 111 1 Master Disk utu 1 tv i Dtfiii A Date and Time Configuration Select the Standard option Select the Date and Time icon The current values for each category are dis played Enter new values through the keyboard Floppy Drive A Floppy Drive 8 Move the cursor to these fields and select the floppy type The settings are 360KB 5114 inch 1 2MB 5114 inch 720KB 3112 inch 1 44...

Page 34: ...ion ofthe WinBIOS Setup main menu to allow WinBIOS to automati cally detectthe IDE drive parameters and report them on this screen Using Auto Detect Hard Disk Only for IDE drives If you select Detect Master and Detect Slave from the Utility section ofthe WinBIOS Setup main menu WinBIOS automatically fmds the IDE hard disk drive parameters WinBIOS places the hard disk drive pa rameters that it find...

Page 35: ... does not specify ifa keyboard is attached to the com puter Rather it specifies if error messages are displayed if a keyboard is not attached This option permits you to configure workstations with no keyboard The settings are Present or Ab sent Primary Display Select this icon to configure the type of monitor attached to the computer The settings are Monochrome Color 40 x 25 Color 80 x 25 VGAIPGAI...

Page 36: ...n ifthe top 1 KB ofthe system programming area beginning at 639K or 0 300 in the system BIOS area in low memory will be used to store hard disk information The set tings are Top DOS IK or 0 3 00 System Boot Up Num Lock When Off this option turns offNum Lockf unction at startup So the numeric keypad can be use as the arrow keys The settings are On or Off Floppy Drive Seek At Boot When this option e...

Page 37: ... boot up IfAlways is chosen the password prompt appears every time the computer is tum on IfSetup is chosen the pass word prompt appears when WinBIOS is executed The settings are Always or Setup Video ROM Shadow COOO 32K When these options are set to Shadow the video ROM area from COOOOh C7FFFh is copied shadowed to the RAM for faster execution The settings are Absent NoShadow or Shadow Shadow xxx...

Page 38: ... Num Lock On On Floppy Drive Seek At Boot Enabled Disabled System Boot Up Sequence A C C A System Boot Up CPU Speed High High External Cache Enabled Disabled Internal Cache Enabled Enabled Password Checking Setup Setup Video Shadow COOO 32K Enabled Disabled Shadow C800 1 6K Disabled Disabled Shadow CCOO 1 6K Disabled Disabled Shadow DOOO 1 6K Disabled Disabled Shadow D400 1 6K Disabled Disabled Sh...

Page 39: ... based on detection of the CPU clock frequency when this option is Disabled B IOS leave these features to be manu ally adjusted by the user Note Listedfeatures on the table areftxed under auto con figuration generally you should not change the settings Oth erwise the mainboard may not work properly Recommend Chip Setup for Different System Clock 25MI lz 33MI lz 40MHz SOMI lz CacheSpeed Options 2 1...

Page 40: ...s PCICLK to ISA SYSCLK Divsor This option sets the SA clock that divide from PC Clock The settings are PCICLKU2 PCICLKU3 or PCICLKU4 Keyboard Clock Divsor This option sets the keyboard clock frequency derive from PCI Clock The settings are PCICLKU2 PCICLKU3 PCICLKU4 or 7 16MHz L2 Cache mode This option sets the external cache scheme The settings are Write Through or Write Back L1Cache mode This op...

Page 41: ...write CPU bus enabled or disabled The settings are Enabled or Disabled Host to DRAM Burst Write This option sets the Host to DRAM Burst write CPU bus to enabled or disabled The settings are Enabled or Disabled Post Write Buffer This option sets the Post Memory Write Buffer enabled or dis abled Enabling this option will enhance system performance The settings are Enabled or Disabled Bus Park This o...

Page 42: ...PCICLK to ISA SYSCLK Divsor Not adjustable PCICLK 4 Keyboard CLOCK Divsor 7 1 6 MHz 7 1 6Mhz L2 Cache mode Wr Back Wr Thru L I Cache mode Wr Thru Wr Thru Main BIOS Cacheable Disabled Disabled Video BIOS Cacheable Enabled Disabled Host to PCI Post Write W S I W S I W S Host to PCI Burst Write Disabled Disabled Host to DRAM Burst Write Disabled Disabled Post Write Buffer Enabled Disabled Bus Park En...

Page 43: ...r Cit Power Management U t l l t t ITrI _ _ _ _ Di sabled Disabled Di sa blltd Di sal led This option sets the mainboard power management function The settings are Enabled or Disabled APM Function This option sets the mainboard APM Advanced Power Manage ment function The settings are Enabled or Disabled Doze Mode Timeout This option sets the timeout length of when the mainboard enters the Doze mod...

Page 44: ... function The set tings are from I min to 14 min or Disabled Monitor PCI Master x This option calls for monitoring of the activity of the PCI Mas ter x The timer will start counting ifEnabled when there is no activity detected This option works in conjunction with the other monitoring functions belows The settings are Enabled or Dis abled Monitor LPT Port Activity This option calls for monitoring ...

Page 45: ...tor 1 0 Region Activity This option calls for monitoring of the activity of the program mable 110 port region The settings are Enabled or Disabled Monitor 1 0 Address This option calls for monitoring of the activity of the 1 0 port address The settings range from IOOh to 3FFh Monitor IRQXX This option calls for monitoring ofthe activity of the IRQxx xx 1 3 4 5 6 7 9 1 0 1 1 1 2 1 4 and 1 5 The set...

Page 46: ...bled Disabled Monitor LPT Port Activity Disabled Disabled Monitor COM Port Activity Disabled Disabled Monitor SA Master DMA Activity Enabled Disabled Monitor IDE Activity Enabled Disabled Monitor FLP Activity Enabled Disabled Monitor YGA Activity Disabled Disabled Monitor KBD Activity Enabled Disabled Monitored I 0 Region Activity Disabled Disabled Monitor l 0 Addres s 0 0 Monitor IRQ 1 5 Disabled...

Page 47: ...led Monitor IRQ9 Disabled Disabled Monitor IRQ8 Disabled Disabled Monitor IRQ7 Disabled Disabled Monitor IRQ6 Disabled Disabled Monitor IRQ5 Disabled Disabled Monitor IRQ4 Disabled Disabled Monitor IRQ3 Enabled Disabled Monitor IRQ Enabled Disabled User s Manual 4 5 ...

Page 48: ...r disabled The settings are Enabled or Disabled PCI Onboard Secondary IDE This option sets the PCI on board secondary IDE controller to be enabled or disabled The settings are Enabled or Disabled PCI OnBoard IDE Speed Mode This option sets PCI on board IDE controller s PIO speed mode The options are Mode I Mode 2 Mode 3 and Disabled PCI IDE Card Present on This option sets the PCI IDE Add on card ...

Page 49: ...E hard disk installed supports block transfer mode This option will enhance the data transfer rate The settings are 2 4 8 16 3 2 64 Auto or Disabled IDE 32 Bit Transfers Mode This option set the IDE 32 bit transfers mode Enabling will enhance data transfer rate But only 32 bit PCI IDE controller is supported on this mainboard The settings are Enabled or Dis abled Primary Master LBA Mode This optio...

Page 50: ...gs are Enabled or Disabled FDC Controller This option sets the use and address ofthe on board floppy drive controller The settings are 3FJH 37 H or Disabled Primary Serial Port This option sets the use and address of the on board primary serial port The settings are 3F8H 3 8H or Disabled Secondary Serial Port This option sets the use and address of the on board secondary serial port The settings a...

Page 51: ...ry IDE IRQ INT B INT B IDE Block Mode Disabled Disabled IDE 32 Bit Transfers Mode Disabled Disabled Primary Master LBA Mode Disabled Disabled Primary Slave LBA Mode Disabled Disabled Secondary Ctrl Drives Present None None Secondary Master LBA Mode Disabled Disabled Secondary Slave LBA Mode Disabled Disabled FDC Controller 3FI H Disabled Primary Serial Port 3F8H Disabled Secondary Serial Port 2F8H...

Page 52: ... can enter a password by 0 typing the password on the keyboard 0 selecting each letter via the mouse or 0 selecting each letter via the pen stylus Pen access must be customized for each specific hardware plat form The password check option is enabled in Advanced Setup by choosing either Always or Setup The password is stored in CMOS RAM The password can be from I to 6 alphanumeric word Please make...

Page 53: ...password confirmation is incorrect an error message ap pears Then please repeat the step above If the new password is entered without error press Esc to return to the WinBIOS Setup Main Menu The password is now stored in CMOS RAM after WinBIOS Setup completes The next time the system boots you will be prompted for the password then Remember the Password Keep a record ofthe new password when the pa...

Page 54: ...a Applications Memory used by the operating system device drivers TSRs and all DOS applications Video Buff er EGA and VGA Video Buffer forMonochrome CGA color and VGA monochrome Video Buffer for CGA EGA color and VGA color Video ROM EGA and VGA Unused Reserved for Adaptor ROMs otherdevices requiring ROMs Used by Adaptor ROMs such as Network Controllers Hard Disk Controllers and SCSI Host Adaptors ...

Page 55: ... and CMOS I 0 ports 080 09F DMA register OAO OBF INTERRUPT controller Slave OCO ODF DMA controller Slave OFO OFF MATH CORPROCESSOR I FO I F8 HARD DISK controller 278 27F PARALLEL port 2 2B0 2DF GRAPHICS adapter controller 2F8 2FF SERIAL ports 2 378 37F PARALLEL port 3B0 3BF MONOCHROME and PRINTER adapter 3C0 3CF EGA adapter 3D0 3DF CGA adapter 3F0 3F7 FLOPPY DISK controller 3F8 3FF SERIAL port Use...

Page 56: ...FRESH request SPEAKER tone generator DMA CHANNEL MAP DMA Channel 0 Available DMA Channel I IBM SDLC DMA Channel 2 FLOPPY DISK adapter DMA Channel 3 Available DMA Channel 4 Cascade for DMA controller 1 DMA Channel 5 Available DMA Channel 6 Available DMA Channel 7 Available 54 User s Manual ...

Page 57: ... KEYBOARD controller 2 Cascade for IRQ 8 1 5 3 SERIAL port 2 4 SERIAL port I 5 PARALLEL port 2 6 FLOPPY DISK adapter 7 PARALLEL port I 8 RTC clock 9 Available 1 0 Available I I Available 1 2 Available 13 MATH coprocessor 1 4 HARD DISK adpater 1 5 Available User s Manual5 5 ...

Page 58: ...Base 64KB Memory Memory failure in first 64KB Failure Timer Not Operational Memory failure in the first 64KB ofmemory or Timer I on the mainboard is not functioning Processor error The CPU on the mainboard generated an error 8042 Gate A20 Failure The keyboard controller 8042 may be bad The BIOS cannot switchto protected mode Processor Exception The CPU generated an exception interrupt interrupt Er...

Page 59: ... Calculating ROM BIOS checksum 07h ROM BIOS checksum passed CMOS shutdown registertest to be done next 08h CMOS shutdown register test done CMOS checksum calculation to be done next 09h The CMOS checksum calculation is done and the CMOS RAM Diagnostic byte has been written CMOS RAM initialization is next ifthe InitializedCMOSAt EveryBoot option is set OAh CMOS RAM is initialized The CMOS RAM statu...

Page 60: ...refresh l ine has been toggled Checking the 1 5u second ON OFF time next 20h The memory refresh period 30u second test has completed Starting the base 64KB memory and address line test next 2 l h The address line test passed Toggling parity next 22h Parity has been toggled The sequential data Read Write teston the base 64KB of system memory is next 23h The base 64KB sequential dataRead Writetest p...

Page 61: ...emory Read Write test next 32h The alternate display memory Read Write test passed Searching for alternate display retrace checking next 34h Video display checking over The display mode will be set next 37h Display mode set Display the power on message 39h New cursorposition read and saved Displaying the Hit DEL message next 3Bh The Hit DEL message has been displayed The virtual mode memory test i...

Page 62: ...d memory size f or memory relocation and shadowing next 5 l h The memory size display was adjusted because ofmemory relocation and shadowing The test ofthe memory above I MB will be done next 52h The testing and initialization ofthe memory above I MB has complete Next saving the memory size information 53h The memory size information has been saved The CPU registers have been saved Entering real m...

Page 63: ...ck has completed Displaying soft errors checking f or a password or bypassing WINBIOS and AMIBIOS Setup next 86h The password as been checked Doing programming before WINBIOS and AM BIOS Setup runs next 87h Programming before WINBIOS and AMIBIOS Setup has completed Uncompressing the WINBIOS and AMIBIOS Setup code and executing WINBIOS and AMIBIOS Setup next 88h Returned from WINBIOS and AMIBIOS Se...

Page 64: ... base addresses have been configured Configuring the RS 232 base 1 0 portaddress next 9Bh The RS 232 base UO port address has been configured Performing any initialization required before the coprocessortest next 9Ch The required initialization before the coprocessortest has completed Initializing the coprocessor next 9Dh The coprocessor has been initialized Doing any required initialization after...

Page 65: ...h Control returned to WINBIOS and AMIBIOS POST from the EOOOOh adaptor ROM Performing anyrequired initialization after EOOOOh adaptor ROM control next AAh Any required initialization after the EOOOOh adaptor ROM had control has completed Displaying the WINBIOS and AMIBIOS system configura tion screen next BOh The WINBIOS and AMIBIOS system configuration is displayed Uncompressingthe WINBIOS and AM...

Page 66: ...erence by one or more ofthe following measures Reorient or relocate the receiving antenna Increase the separation between the equipment and receiver Connect the equipment into an outlet on a circuit different from that to which the receiver is connected Consult the dealer or an experienced radio television technician for help and for additional suggestions The user may find the following booklet p...

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