Sharp SD-AS10, Service Manual

Page: 88 / 188

SD-AS10
6 – 11
[2] Schematic diagram
Figure 6-11 SCHEMATIC DIAGRAM (1/18)
D_+3.3V
D_+3.3V
D_+3.3V
D_+3.3V
A_+2.5V
VDD_+2.5V AVDD_+2.5V A_+2.5V
AVDD_+2.5V
VDD_+2.5V
D_+2.5V
D_+5V
D_+5V
0.01
10K
KDS160
KDS160
74V2GU04
INVERTER RESISTO
STG3157C
6
5
4 3
2
1
5.6K
0.1
0.1
0.1
220
2.2 µH
0.1
10/16
220
0.1
220
KDS160
IX0446AW
VOLTAGE
REGULATOR
3.3V
REGULATOR
2
0.1
1
10/16
1K
1
1K
10K
STG3157C
HIGH
SPEED
SWITCH
HIGH SPEED
SWITCH
HIGH SPEED
SWITCH
6
5
4 3
2
1
STG3157C
6
5
4 3
2
1
10K
10K
10K
10K
10K
10K
100
0.1
0.1
10/16
1K
220
220
3.3K 10K 3.3K 3.3K
9
8
7
6
5
4
3
2
1
47K
3.3K
3.3K
10K
3.3K
100
68P(CH)
47K
1K
0.1
1
L4931Z33
2
10/16
KDS160
0.1
2.2 µH
1
1M
22P(CH)
22P(CH)
0.001
0.01
470P
2.2/50
0.1
74HC07AF
BUFFER
AMP.
10/16
1
0.1
4.7K 4.7K
1
0.1
1
0.1
1
0.1
0.1
100
330
330
330
33K
10K
CS493264
9
10
11
12
10
11
12
13
14
15
44 43 42 41 40
39
38
37
36
35
34
33
32
31
30
29
39
16
17
18 19 20 21 22 23 24 25 26 27
27
28
28
8
7
4 3 2 1
8 6
7 5
1 2 3 4
5
6
7
8 9 10 11 12 13 14
1 2 3 4
5 6
6
3
1
1
3
SDATA1
DVS_CS DVS_CLK
SCLK
SCLK
LRCK
AUDATA0_OUT
AUDATA0_IN
AUDATA1_IN AUDATA0_IN
DVS_SELECTOR
AUDATA1_OUT
DVS_DATA
AUDATA1_IN
_DSP_INTREQ _DSP_SCDOUT _DSP_CS
EX_CLK
_DSP_SCDIN
DSP_CS
_DSP_SCDIN
DSP_SCCLK DSP_INTREQ
_DSP_INTREQ
_DSP_SCDOUT
_DSP_CS
DSP_SCDIN DSP_SCDOUT
_DSP_SCCLK
DSP_RESET
LRCK SCLK
MCLK
/EMWR
/EMOE
/EXTMEM
EMAD0
EMAD1
_DSP_SCCLK
EMAD5
EMAD3
EMAD6
EMAD4
EMAD7
EMAD2
AUDATA2
LRCK
SDATA1
LRCK SCLK
(C/LFE)
(SL/SR)
TEST(NC)
RESET
VSS6
STEREO
MUTE_EXT
VDD6
CMODE
DVS_ENABLE
DVS_CLOCK
DVS_DATA
BIST_DONE
TEST
VDD5
VSS5
FMT2
FMT1
FMT0
BIST_FAIL
TEST
VSS4
PRG4
PRG3
PRG2
PRG1
PRG0
VDD4
PLLSTOP
CLOCK_SW PLL PDO
VCNT
R
CLOCK
TEST
PLL
MCLOCK
PLL0
PLL1 VSS3
VDD3(I/O)
AVDD
AVSS
(BIST_MODE)
TEST
(SCAN_EN)
TEST
(SCAN_MODE)
TEST
SCLOCK(BITCLOCK)
LRCLOCK
VSS1
SDI2(C/LFE)
SDI1(LS/RS)
SDI0(L/R)
SDO
VDD(I/O)
D
GND
D_GND
12.288
MHz
1A
1Y
2A
2Y 3A
3Y
VCC
SCLKN2
LRCLKN2
SDATAN2
VCC
GND
SCCLK
SCDIN
SCDOUT CS INTREQ EXTMEM SDATAN1 SCLKN1 LRCLKN1
D0
D1
D2
D3
D4
D5
D6
D7
RD
WR
XMT958
MCLK
SCLK
LRCLK
AUDATA0 AUDATA1
AUDATA2
CLKIN
CLKSEL
FILT2
FILT1
RESET
DD
DC
AGND
VA
DGND3
DGND2
DGND1
VD3
VD2
VD1
MAIN PWB-A1 (1/4)
3.3K
10K
10K
10K
10K
10K
10K
10K
10K
0
100/16
180P(CH)
18 19 16 17 14 13 15 20 21 22 23 24
36
39 38
38
23
37
35
34
33
32
31
30
29
28
27
26
25
44 43 42 41 48 47 46 45 40
LC83210W
DVS
DSP
+B
+B
+B
+B
+B
+B
+B
+B
+B +B
+B
+B
+B
+B
+B
+B
+B
+B
+B
+B
+B
+B
+B
+B
+B +B
+B +B
R105
R108
R109
R110
R111
R112
R113
R107
R106
L101
C101
C139
C163
IC114
IC115
IC116
R103 R104
R101
R102
C184
C140
C102
C167
IC101
R126
R125
R123 R124
R121
R120
C107
C106
R119
C108
C105
C150
C104
C142
R118
C127 C156
C141
C103
R114 R117 R115 R116
C191
C192 C129 C190
L110
R136 R135
R167
R165
C128
C160
R132
R131
R161
R160
R150
C122
R162
R164
C153
R176
R177
R178
R180
C199
C121
R179
R182
C125
C126
XL101
R148
IC103
C155
C124
L103
C123
R151
IC104
R152
R188
R140
D111
R153
C152
C154
D105
C180
C181
D106
D110
IC113
IC112
C118 C182
IC105
A
B
C
D
E
F
G
H
1 2 3 4 5 6
NOTES ON SCHEMATIC DIAGRAM can be found on page 5-1.