SD-AS10
4 – 7
STG3157C
HIGH SPEED
SWITCH
HIGH SPEED
SWITCH
HIGH SPEED
SWITCH
6
5
4
3
2
1
STG3157C
STG3157C
6
5
4
3
2
1
6
5
4
3
2
1
LC83210W
DVS
9
8
7
6
5
4
3
2
1
9
10
11
12
13
14
15
16
17
36
35
34
39
31
30
29
18 19 20 21 22 23 24 25 26 27 28
28
29
44 43 42 41 40
40
8
7
4
2
1
8 7 6
3 2
4
5
6
7
8 9
11 12 13
1
2
5
6
6
2
2
2
1
3
3
1
EX_CLK
SDATA1
SCLK
LRCK
SCLK
SDATA1
/EXTMEM
_DSP_INTREQ
_DSP_CS
_DSP_SCDOUT
/EMOE
_DSP_SCDIN
EMAD0
EMAD1
EMAD3
EMAD2
EMAD4
EMAD5
EMAD6
EMAD7
_DSP_SCCLK
_DSP_SCCLK
DSP
INTREQ
DSP_SCCLK
DSP_ABOOT
DSP_INTREQ
AUDATA2
DSP_RESET
LRCK
SCLK
MCLK
AUDATA1
AUDATA0
_DSP_CS
_DSP_SCDIN
DSP_SCDIN
DSP
SCDOUT
DSP_CS
LRCK
VDD(I/O)
SDO
SDI0(L/R)
SDI1(LS/RS)
SDI2(C/LFE)
VSS1
LRCLOCK
SCLOCK(BITCLOCK)
TEST
(SCAN_MODE)
TEST
(SCAN_EN)
TEST
(BIST_MODE)
AVSS
VDD3(I/O)
VSS3
PLL1
PLL
TEST
CLOCK
PLL CLOCK_SW
VDD4
PRG0
PRG1
PRG2
PRG3
PRG4
VSS4
TEST
BIST_FAIL
VSS5
DVS_DATA
DVS_CLOCK
DVS_ENABLE
VDD6
MUTE_EXT
STEREO
VSS6
CS493264
74HC07AF
BUFFER
AMP.
74V
INV
RES
SCLKN2
LRCLKN2
SDATAN2
SCCLK
SCDIN
SCDOUT
CS
INTREQ
EXTMEM
SDATAN1
SCLKN1
LRCLKN1
D0
D1
D2
D3
D4
D5
D6
D7
RD
MCLK
SCLK
LRCLK
AUDATA0
AUDATA1
39 AUDATA2
CLKIN
CLKSEL
RESET
AGND
VA
DGND3
DGND2
DGND1
VD3
VD2
VD1
IX0446AW VOLTAGE
REGULATOR
L4931Z33
3.3V REGULATO
10
11
12
19 20 21
13
17
24
36
32
31
30
29
28
27
26
25
44 43
41
48 47 46 45
40 39
37
XL101
12.288
MHz
DSP
+2.5V(A)
+3.3V(D)
+2.5V(D)
+5V(D)
+5V(D)
D_+3.3V
+2.5V(D)
+2.5V(D)
+2.5V(D)
+3.3V(D)
IC101
IC
IC104
IC114
IC115
IC116
L110
IC105
IC113
IC112
D105
D106
Figure 4-7 BLOCK DIAGRAM (7/18)
Summary of Contents for SD-AS10
Page 24: ...SD AS10 3 9 ASSEMBLY SEQUENCE 1 FIX ITEM 148 157 TO ITEM 115 148 157 115 5 ...
Page 50: ...SD AS10 3 35 178 ASSEMBLY SEQUENCE 1 FIX ITEM 178 TO MAIN CHASSIS ASSY 31 ...
Page 53: ...SD AS10 3 38 M E M O ...
Page 75: ...SD AS10 5 4 6 6 ...
Page 186: ... M E M O SD AS10 ...
Page 187: ... M E M O SD AS10 ...