MD-R2
– 58 –
Figure 58-1 BLOCK DIAGRAM OF IC
IC1101 VHiiR3R55//-1:RF Signal Control (IR3R55)
IC1201 VHiLR376481-1:ENDEC/ATRAC (LR376481)
Figure 58-2 BLOCK DIAGRAM OF IC
1
2
3
4
5
6
7
8
9
10
11
12
27
26
25
RF1
RF2
RF3
RF4
REFI
REFO
RFADD
TCGI
AIN
BIN
EIN
FIN
36
35
34
33
32
31
30
29
28
ADIPI
ADIPO
NC
ADLPFO
22KO
22KI
WBO
TCGO
AOUT
BOUT
EOUT
FOUT
POUT
GOUT
ATTR
EFMAGI
EFMAGC
AGND
AVCC
EFMI
EFMO
RF2-1
ADAGI
ADAGC
BAIS
AVCC
XSTBY
XDISC
AGND
XSGAIN
DGND
DTEMP
LATCH
CLOCK
DATA
DVCC
LOGIC
HPF
LPF
BIAS
ADIP
AGC
DIFF
DIFF
EFM
AGC
RESISTOR & SW
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
TOTMON
TEMON
SBCK
SBO
SBSY
SFSY
FOK
SENSE
COUT
MCCK
DINTX
VDD1
DGND
RSTX
SYD0
SYD1
SYD2
SYD3
SYD4
SYD5
SYD6
SYD7
SYWRX
SYRDX
SYRS
EFMO
PLCK
ACRCER
TCRS
RAD0
RAD1
RAWEX
RARASX
RAA9
RAD3
RAD2
RACASX
DGND
RAOEX
RAA8
RAA7
RAA6
RAA5
RAA4
VDD2
RAA10
RAA0
RAA1
RAA2
RAA3
FEMON
DADATA
ADDATA
DFCK
BCLK
LRCK
DGND
VDD3
DOUT
DIN
XO
XI
DGND
VDD1
VPO
VXI
CDBCLK
CDLRCK
CDDATA
TEST4
TEST3
TESO1
EXPORT1
EXPORT0
X700KO
EFMMON
AVCC
EFMI
AGND
AIN
EIN
TCG
BIN
FIN
VBAT
WBI
VDD1
DGND
TEST0
TEST1
TEST2
X176KO
FODRF
FODRR
TRDRF
TRDRR
SLDRF
SLDRR
SPDRF
SPDRR
LR376481