LC-32SV502B/LC-42SV502B/LC-42SV602B/LC-46SV602B/LC-46SV502L
54
· Hand-Held Equipment
2.7 U101(CXD2828ER)
General Description
The Sony CXD2828ER is an ISDB-T and SBTVD-T demodulator that conforms to the ARIB STD-B31 standards. It receives signal from the tuner and
outputs signal in TS format after demodulation.
Features
・
All internal clocks derived from signal fixed 41MHz/20.5MHz frequency crystal (<±100ppm).
・
High performance differential ADC
・
Fast 400kHz I2C compatible bus interface
・
Gateway I2C interface for dedicated tuner control
・
Automatic IF AGC and optional programmable GPIO interface
・
Configurable parallel and serial MPEG-2 TS outputs
・
Built-in de-interleave memory
(
No external memory required
)
・
3.3V, 2.5V, 1.2V supplies
・
Temperature range -20 to +85
℃
・
48 pin VQFN 7mm x 7mm package (0.5mm pin pitch)
・
Very low operating power consumption (Clear channel)
ISD
B-T
:
180mW (typ.)
・
Power standby mode (Shutdown: Clock stop mode)
Sleep
:
25mW(typ.)
Shutdown
:
under 1mW(typ.)
Features ISDB-T
・
Conforms to ARIB STD-B31
・
Supports Low-IF, 57MHz-IF tuner.
・
Excellent phase noise resistance
・
Excellent multipath equalization performance
・
Automatic detection of mode/guard internal lengths.
・
EWS (Emergency Warning System) flag output
・
Read function of AC Carrier information corresponding to the earthquake broadcasting. (ARIB STD-B31 v1.8)
Applications
・
Set Top boxes
・
PC TV
・
PVRs and recordable DVD players
2.8 U413(M24C02)
General Description
These I²C-compatible electrically erasable programmable memory (EEPROM) devices are organized as 2048/1024/512/256/128 x 8 (M24C16, M24C08,
M24C04, M24C02 and M24C01).
In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. ECOPACK® packages are Lead-free and RoHS
compliant.
ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
I²C uses a two-wire serial interface, comprising a bidirectional data line and a clock line. The devices carry a built-in 4-bit Device Type Identifier code
(1010) in accordance with the I²C bus definition.
The device behaves as a slave in the I²C protocol, with all memory operations synchronized by the serial clock. Read and Write operations are initiated
by a Start condition, generated by the bus master. The Start condition is followed by a device select code and Read/Write bit (RW), terminated by an
acknowledge bit.
When writing data to the memory, the device inserts an acknowledge bit during the 9th bit time, following the bus master’s 8-bit transmission. When data
is read by the bus master, the bus master acknowledges the receipt of the data byte in the same way. Data transfers are terminated by a Stop condition
Summary of Contents for LC-32SV502B
Page 5: ...LC 32SV502B LC 42SV502B LC 42SV602B LC 46SV602B LC 46SV502L 5 ...
Page 17: ...LC 32SV502B LC 42SV502B LC 42SV602B LC 46SV602B LC 46SV502L 17 LC 32SV502B ...
Page 58: ...LC 32SV502B LC 42SV502B LC 42SV602B LC 46SV602B LC 46SV502L 58 ...
Page 59: ...LC 32SV502B LC 42SV502B LC 42SV602B LC 46SV602B LC 46SV502L 59 DDR2 Ball Map ...
Page 60: ...LC 32SV502B LC 42SV502B LC 42SV602B LC 46SV602B LC 46SV502L 60 ...
Page 134: ...LC 32SV502B LC 42SV502B LC 42SV602B LC 46SV602B LC 46SV502L 134 2 CABINET PARTS ...
Page 136: ...LC 32SV502B LC 42SV502B LC 42SV602B LC 46SV602B LC 46SV502L 136 Only For LC 32SV502B ...