Sharp LC-24LE250V-BK, Service Manual

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LC-22LE250
LC-24LE250
CLE input pin. The on-chip Program/Erase Controller automates all read, program and erase functions
including pulse repetition, where required, and internal verification and margining of data.
A WP# pin is available to provide hardware protection against program and erase operations.
The output pin RB# (open drain buffer) signals the status of the device during each operation. In a
system with multiple memories the RB# pins can be connected all together to provide a global status
signal. Each block can be programmed and erased up to 100,000 cycles with ECC (error correction
code) on. To extend the lifetime of Nand Flash devices, the implementation of an ECC is mandatory.
The chip supports CE# don't care function. This function allows the direct download of the code from
the NAND Flash memory device by a microcontroller, since the CE# transitions do not stop the read
operation. In addition, device supports ONFI 1.0 specification.
The copy back function allows the optimization of defective blocks management: when a page
program operation fails the data can be directly programmed in another page inside the same array
section without the time consuming serial data insertion phase. Copy back operation automatically
executes embedded error detection operation: 1 bit error out of every 528-byte (x8) or 1 bit error out of
every 264-word (x16) can be detected. With this feature it is no longer necessary to use an external to
detect copy back operation errors. Multiplane copy back is also supported, both with traditional and
ONFI 1.0 protocols. Data read out after copy back read (both for single and multiplane cases) is
allowed. In addition, Cache program and multi cache program operations improve the programming
throughput by programming data using the cache register.
The devices provide two innovative features: page re-program and multiplane page re program. The
page re-program allows to re-program one page. Normally, this operation is performed after a
previously failed page program operation. Similarly, the multiplane page reprogram allows to
re-program two pages in parallel, one per each plane. The first page must be in the first plane while the
second page must be in the second plane; the multiplane page re-program operation is performed after a
previously failed multiplane page program operation. The page re-program and multiplane page
re-program guarantee improve performance, since data insertion can be omitted during re-program
operations, and save ram buffer at the host in the case of program failure. The devices, available in the
TSOP48 (12X20mm) package, support the ONFI1.0 specification and come with four sequrity features:
-OTP (one time programmable) area, which is a restricted access area where sensitive data/code
can be stored permantely.
-Serial number (unique identifier), which allows the devices to be uniquely indentified.
-Read ID2 extension
These security features are subject to an NDA (non-disclosure agreement) and are, therefore, no
described in the datasheet. For more details about them, contact your nearest Hynix sales office.