Sharp LC-24LE250V-BK, Service Manual

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LC-24LE250
LC-22LE250
27
Table 10: Recommended operating conditions
6. 1Gb DDR3 SDRAM
Hynix H5TQ1G630FA
a) Description
The H5TQ1G6(8)3DFR-xxx series are a 1,073,741,824-bit CMOS Double Data Rate III
(DDR3) Synchronous DRAM, ideally suited for the main memory applications which
requires large memory density and high bandwidth. Hynix 1Gb DDR3 SDRAMs offer fully
synchronous operations referenced to both rising and falling edges of the clock. While all
addresses and control inputs are latched on the rising edges of the CK (falling edges of the
CK), Data, Data strobes and Write data masks inputs are sampled on both rising and falling
edges of it. The data paths are internally pipelined and 8-bit prefetched to achieve very high
bandwidth.
b) Features
• DQ Power & Power supply : VDD & VDDQ = 1.5V +/- 0.075V
• DQ Ground supply : VSSQ = Ground
• Fully differential clock inputs (CK, CK) operation
• Differential Data Strobe (DQS, DQS)
• On chip DLL align DQ, DQS and DQS transition with CK transition
• DM masks write data-in at the both rising and falling edges of the data strobe
• All addresses and control inputs except data, data strobes and data masks latched on the
rising edges of the clock
• Programmable CAS latency 6, 7, 8, 9, 10, 11, 12, 13 and 14 supported
• Programmable additive latency 0, CL-1, and CL-2 supported
• Programmable CAS Write latency (CWL) = 5, 6, 7, 8, 9, 10
• Programmable burst length 4/8 with both nibble sequential and interleave mode
• Programmable PASR(Partial Array Self-Refresh) for Digital consumer Applications.