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95
LC-22DV510
LC-24DV510
17mb60-4
MB60_HW_TEAM
9
RAM&SPI_FLASH
24-05-2011_13:45
8
7
6
5
4
3
2
1
A
B
C
D
E
F
A X M
1
2
3
4
5
6
7
8
A
B
C
D
E
F
A3
PROJECT NAME :
VESTEL
SCH NAME :
DRAWN BY :
TOTAL SHEET:
R1321
56R
R1319
56R
56R
R1315
56R
R1609
8
7
6
5
4
3
2
1
R4
R3
R2
R1
R1602
56R
56R
R1374
8
7
6
5
4
3
2
1
R4
R3
R2
R1
56R
R1314
56R
R1335
R1330
56R
R1332
56R
56R
R1333
56R
R1331
R1313
56R
R1327
56R
56R
R1325
56R
R1317
56R
R1603
56R
R1613
8
7
6
5
4
3
2
1
R4
R3
R2
R1
R1608
56R
8
7
6
5
4
3
2
1
R4
R3
R2
R1
R1610
56R
8
7
6
5
4
3
2
1
R4
R3
R2
R1
56R
R1328
56R
R1612
8
7
6
5
4
3
2
1
R4
R3
R2
R1
DDR18V
AVDD_DDR
R1356
1k
100n
C683
10V
2
1
R1365
1k
DDR18V
DDR18V
3V3_STBY
DDR18V
1k
R1355
10V
C687
100n
2
1
1k
R1364
R1354
1k
100n
C689
10V
2
1
R1363
1k
100n
10V
C723
2
1
100n
C721
10V
2
1
C722
10V
100n
2
1
C719
100n
10V
2
1
10V
100n
C720
2
1
C717
10V
100n
2
1
DDR18V
100n
10V
C718
2
1
C715
10V
100n
2
1
100n
2
1
10V
C716
10V
C713
100n
2
1
100n
C714
10V
2
1
100n
10V
C711
2
1
100n
C712
10V
2
1
10V
100n
C709
2
1
1V8_VCC
DDR18V
DDR18V
60R
F181
R1944
150R
R1611
56R
8
7
6
5
4
3
2
1
R4
R3
R2
R1
R1346
56R
56R
R1373
8
7
6
5
4
3
2
1
R4
R3
R2
R1
56R
R1349
56R
R1350
R1323
56R
R1375
56R
8
7
6
5
4
3
2
1
R4
R3
R2
R1
56R
R1377
8
7
6
5
4
3
2
1
R4
R3
R2
R1
R1378
56R
8
7
6
5
4
3
2
1
R4
R3
R2
R1
R1380
56R
8
7
6
5
4
3
2
1
R4
R3
R2
R1
R1370
56R
8
7
6
5
4
3
2
1
R4
R3
R2
R1
56R
R1368
8
7
6
5
4
3
2
1
R4
R3
R2
R1
R1366
56R
8
7
6
5
4
3
2
1
R4
R3
R2
R1
R1367
56R
8
7
6
5
4
3
2
1
R4
R3
R2
R1
56R
R1369
8
7
6
5
4
3
2
1
R4
R3
R2
R1
HY5PS121621C
U154
G8
G2
H7
H3
H1
H9
F1
F7
E8
F3
F9
C8
C2
D7
D3
D1
D9
B1
B9
B7
A8
B3
A2
E2
L1
R3
R7
R8
M8
M3
M7
N2
N8
N3
N7
P2
P8
P3
M2
P7
R2
L2
L3
K7
L7
K3
L8
K2
J8
K8
K9
A3
E3
J3
N1
P9
A7
B2
B8
D2
D8
E7
F2
F8
H2
H8
J7
J2
A9
C1
C3
C7
C9
E9
G1
G3
G7
G9
A1
E1
J9
M9
R1
J1
VDDL
VDD5
VDD4
VDD3
VDD2
VDD1
VDDQ10
VDDQ9
VDDQ8
VDDQ7
VDDQ6
VDDQ5
VDDQ4
VDDQ3
VDDQ2
VDDQ1
VREF
VSSDL
VSSQ10
VSSQ9
VSSQ8
VSSQ7
VSSQ6
VSSQ5
VSSQ4
VSSQ3
VSSQ2
VSSQ1
VSS5
VSS4
VSS3
VSS2
VSS1
ODT
CK_P
CK
CKE
CS_P
WE_P
CAS_P
RAS_P
BA1
BA0
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
NC6
NC5
NC4
NC3
NC2
NC1
UDM
UDQS_P
UDQS
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
LDM
LQDS_P
LQDS
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
R1371
56R
8
7
6
5
4
3
2
1
R4
R3
R2
R1
U155
HY5PS121621C
G8
G2
H7
H3
H1
H9
F1
F7
E8
F3
F9
C8
C2
D7
D3
D1
D9
B1
B9
B7
A8
B3
A2
E2
L1
R3
R7
R8
M8
M3
M7
N2
N8
N3
N7
P2
P8
P3
M2
P7
R2
L2
L3
K7
L7
K3
L8
K2
J8
K8
K9
A3
E3
J3
N1
P9
A7
B2
B8
D2
D8
E7
F2
F8
H2
H8
J7
J2
A9
C1
C3
C7
C9
E9
G1
G3
G7
G9
A1
E1
J9
M9
R1
J1
VDDL
VDD5
VDD4
VDD3
VDD2
VDD1
VDDQ10
VDDQ9
VDDQ8
VDDQ7
VDDQ6
VDDQ5
VDDQ4
VDDQ3
VDDQ2
VDDQ1
VREF
VSSDL
VSSQ10
VSSQ9
VSSQ8
VSSQ7
VSSQ6
VSSQ5
VSSQ4
VSSQ3
VSSQ2
VSSQ1
VSS5
VSS4
VSS3
VSS2
VSS1
ODT
CK_P
CK
CKE
CS_P
WE_P
CAS_P
RAS_P
BA1
BA0
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
NC6
NC5
NC4
NC3
NC2
NC1
UDM
UDQS_P
UDQS
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
LDM
LQDS_P
LQDS
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
56R
R1379
8
7
6
5
4
3
2
1
R4
R3
R2
R1
16V
22u
C782
R1183
4k7
F172
330R
2
1
100n
C658
10V
2
1
TP14
1
TP12
1
U158
MX25L512
8
7
6
5
4
3
2
1 CS#
SO
WP#
GND
SI
SCLK
HOLD#
VCC
TP40
1
TP15
1
TP11
1
TP41
1
FLASH_WPN
SPI_SCK
SPI_SDO
SPI_CSN_1
100R
R1248
2
1
SPI_SDI
MSD9WB7PX-2
U157
C10
A22
A9
B23
B9
A23
C9
C23
B8
A24
B22
C8
B24
B7
C13
A19
A12
B19
C20
B12
C19
A13
B14
C18
C14
A18
B18
B13
B17
C15
A16
C16
A15
B15
B16
C17
C12
B11
C21
B20
B10
A10
A21
B21
C22
C11
E23
U24
D24
V25
D25
V24
D23
W25
C25
W24
V23
C24
W23
B25
H23
P24
G24
R23
R24
G25
P23
H24
J25
N23
J24
N24
N25
J23
M25
K23
L24
L23
K24
K25
M23
M24
G23
F25
T23
R25
F23
E24
T24
T25
U23
F24
D22
MVREF
B_ODT
B_BADR[2]
B_BADR[1]
B_BADR[0]
B_CASZ
B_RASZ
B_WEZ
B_CKE
B_MCLKZ
B_MCLK
B_DQM[1]
B_DQM[0]
B_DQSB[1]
B_DQS[1]
B_DQSB[0]
B_DQS[0]
B_MDATA[15]
B_MDATA[14]
B_MDATA[13]
B_MDATA[12]
B_MDATA[11]
B_MDATA[10]
B_MDATA[9]
B_MDATA[8]
B_MDATA[7]
B_MDATA[6]
B_MDATA[5]
B_MDATA[4]
B_MDATA[3]
B_MDATA[2]
B_MDATA[1]
B_MDATA[0]
B_MADR[13]
B_MADR[12]
B_MADR[11]
B_MADR[10]
B_MADR[9]
B_MADR[8]
B_MADR[7]
B_MADR[6]
B_MADR[5]
B_MADR[4]
B_MADR[3]
B_MADR[2]
B_MADR[1]
B_MADR[0]
A_ODT
A_BADR[2]
A_BADR[1]
A_BADR[0]
A_CASZ
A_RASZ
A_WEZ
A_MCLKE
A_MCLKZ
A_MCLK
A_DQM[1]
A_DQM[0]
A_DQSB[1]
A_DQS[1]
A_DQSB[0]
A_DQS[0]
A_MDATA[15]
A_MDATA[14]
A_MDATA[13]
A_MDATA[12]
A_MDATA[11]
A_MDATA[10]
A_MDATA[9]
A_MDATA[8]
A_MDATA[7]
A_MDAT[6]
A_MDATA[5]
A_MDATA[4]
A_MDATA[3]
A_MDATA[2]
A_MDATA[1]
A_MDATA[0]
A_MADR[13]
A_MADR[12]
A_MADR[11]
A_MADR[10]
A_MADR[9]
A_MADR[8]
A_MADR[7]
A_MADR[6]
A_MADR[5]
A_MADR[4]
A_MADR[3]
A_MADR[2]
A_MADR[1]
A_MADR[0]
1
C710
100n
10V
2
1
1k
R1357
SPI_SDI
SPI_SDI_1
3V3_STBY
D165
1N4148
2
1
R1358
1k
R1943
150R
D1
C15V
2
1
AA_DDR2_DQSB0
AA_DDR2_DQSB0
BB_BADR_BA2
BB_BADR_BA2
BB_MCLK
BB_MCLK
BB_MCLKZ
BB_MCLKZ
BB_DDR2_DQSB1
BB_DDR2_DQSB1
BB_DDR2_DQS1
BB_DDR2_DQS1
BB_DDR2_DQSB0
BB_DDR2_DQSB0
BB_DDR2_DQS0
BB_DDR2_DQS0
BB_DDR2_DQM0
BB_DDR2_DQM0
BB_DDR2_DQM1
BB_DDR2_DQM1
BB_BADR_BA0
BB_BADR_BA0
BB_BADR_BA1
BB_BADR_BA1
BB_ODT
BB_ODT
BB_MCLKE
BB_MCLKE
BB_WEZ
BB_WEZ
BB_RASZ
BB_RASZ
BB_CASZ
BB_CASZ
BB_MDATA15
BB_MDATA15
BB_MDATA14
BB_MDATA14
BB_MDATA13
BB_MDATA13
BB_MDATA12
BB_MDATA12
BB_MDATA11
BB_MDATA11
BB_MDATA10
BB_MDATA10
BB_MDATA9
BB_MDATA9
BB_MDATA8
BB_MDATA8
BB_MDATA7
BB_MDATA7
BB_MDATA6
BB_MDATA6
BB_MDATA5
BB_MDATA5
BB_MDATA4
BB_MDATA4
BB_MDATA3
BB_MDATA3
BB_MDATA2
BB_MDATA2
BB_MDATA1
BB_MDATA1
BB_MDATA0
BB_MDATA0
BB_MADR12
BB_MADR12
BB_MADR11
BB_MADR11
BB_MADR10
BB_MADR10
BB_MADR9
BB_MADR9
BB_MADR8
BB_MADR8
BB_MADR7
BB_MADR7
BB_MADR6
BB_MADR6
BB_MADR5
BB_MADR5
BB_MADR4
BB_MADR4
BB_MADR3
BB_MADR3
BB_MADR2
BB_MADR2
BB_MADR1
BB_MADR1
BB_MADR0
BB_MADR0
AA_BADR_BA2
AA_BADR_BA2
AA_MCLK
AA_MCLK
AA_MCLKZ
AA_MCLKZ
AA_DDR2_DQSB1
AA_DDR2_DQSB1
AA_DDR2_DQS1
AA_DDR2_DQS1
AA_DDR2_DQS0
AA_DDR2_DQS0
AA_DDR2_DQM0
AA_DDR2_DQM0
AA_DDR2_DQM1
AA_DDR2_DQM1
AA_BADR_BA0
AA_BADR_BA0
AA_BADR_BA1
AA_BADR_BA1
AA_ODT
AA_ODT
AA_WEZ
AA_WEZ
AA_RASZ
AA_RASZ
AA_CASZ
AA_CASZ
AA_MDATA15
AA_MDATA15
AA_MDATA14
AA_MDATA14
AA_MDATA13
AA_MDATA13
AA_MDATA12
AA_MDATA12
AA_MDATA11
AA_MDATA11
AA_MDATA10
AA_MDATA10
AA_MDATA9
AA_MDATA9
AA_MDATA8
AA_MDATA8
AA_MDATA5
AA_MDATA5
AA_MDATA2
AA_MDATA2
AA_MDATA0
AA_MDATA0
AA_MADR12
AA_MADR12
AA_MADR11
AA_MADR11
AA_MADR10
AA_MADR10
AA_MADR9
AA_MADR9
AA_MADR8
AA_MADR8
AA_MADR7
AA_MADR7
AA_MADR6
AA_MADR6
AA_MADR5
AA_MADR5
AA_MADR4
AA_MADR4
AA_MADR3
AA_MADR3
AA_MADR2
AA_MADR2
AA_MADR1
AA_MADR1
AA_MADR0
AA_MADR0
A_MADR12
A_MADR12
A_MADR11
A_MADR11
A_MADR10
A_MADR10
A_MADR9
A_MADR9
A_MADR8
A_MADR8
A_MADR7
A_MADR7
A_MADR6
A_MADR6
A_MADR5
A_MADR5
A_MADR4
A_MADR4
A_MADR3
A_MADR3
A_MADR2
A_MADR2
A_MADR1
A_MADR1
A_MADR0
A_MADR0
A_MDATA0
A_MDATA0
B_MDATA15
B_MDATA15
B_MDATA13
B_MDATA13
B_MDATA14
B_MDATA14
B_MDATA12
B_MDATA12
B_MDATA10
B_MDATA10
B_MDATA11
B_MDATA11
B_MDATA9
B_MDATA9
B_MDATA7
B_MDATA7
B_MDATA8
B_MDATA8
B_MDATA6
B_MDATA6
B_MDATA4
B_MDATA4
B_MDATA5
B_MDATA5
B_MDATA3
B_MDATA3
B_MDATA1
B_MDATA1
B_MDATA2
B_MDATA2
B_MADR12
B_MADR12
B_MDATA0
B_MDATA0
B_MADR10
B_MADR10
B_MADR11
B_MADR11
B_MADR8
B_MADR8
B_MADR9
B_MADR9
B_MADR6
B_MADR6
B_MADR7
B_MADR7
B_MADR4
B_MADR4
B_MADR5
B_MADR5
B_MADR2
B_MADR2
B_MADR3
B_MADR3
B_MADR0
B_MADR0
B_MADR1
B_MADR1
MVREF
MVREF
A_BADR_BA2
A_BADR_BA2
A_DDR2_DQSB1
A_DDR2_DQSB1
A_DDR2_DQS1
A_DDR2_DQS1
A_DDR2_DQSB0
A_DDR2_DQSB0
A_DDR2_DQS0
A_DDR2_DQS0
A_DDR2_DQM0
A_DDR2_DQM0
A_DDR2_DQM1
A_DDR2_DQM1
A_BADR_BA0
A_BADR_BA0
A_BADR_BA1
A_BADR_BA1
A_ODT
A_ODT
A_MCLKE
A_MCLKE
A_WEZ
A_WEZ
A_RASZ
A_RASZ
A_CASZ
A_CASZ
B_BADR_BA2
B_BADR_BA2
B_MCLK
B_MCLK
B_MCLKZ
B_MCLKZ
B_DDR2_DQSB1
B_DDR2_DQSB1
B_DDR2_DQS1
B_DDR2_DQS1
B_DDR2_DQSB0
B_DDR2_DQSB0
B_DDR2_DQS0
B_DDR2_DQS0
B_DDR2_DQM0
B_DDR2_DQM0
B_DDR2_DQM1
B_DDR2_DQM1
B_BADR_BA0
B_BADR_BA0
B_BADR_BA1
B_BADR_BA1
B_ODT
B_ODT
B_MCLKE
B_MCLKE
B_WEZ
B_WEZ
B_RASZ
B_RASZ
B_CASZ
B_CASZ
A_MDATA9
A_MDATA9
A_MDATA2
A_MDATA2
A_MDATA5
A_MDATA5
A_MDATA7
A_MDATA7
A_MDATA8
A_MDATA8
A_MDATA10
A_MDATA10
A_MDATA11
A_MDATA11
A_MDATA12
A_MDATA12
A_MDATA13
A_MDATA13
A_MDATA14
A_MDATA14
A_MDATA15
A_MDATA15
A_MADR13
A_MADR13
AA_MADR13
AA_MADR13
A_MCLKZ
A_MCLKZ
A_MCLK
A_MCLK
B_MADR13
B_MADR13
BB_MADR13
BB_MADR13
AA_MCLKE
AA_MCLKE
A_MDATA6
A_MDATA6
AA_MDATA6
AA_MDATA6
A_MDATA1
A_MDATA1
AA_MDATA1
AA_MDATA1
A_MDATA3
A_MDATA3
AA_MDATA3
AA_MDATA3
A_MDATA4
A_MDATA4
AA_MDATA4
AA_MDATA4
AA_MDATA7
AA_MDATA7
SERIAL FLASH
22R
OPTIONAL
COMMON
22R
22R
22R
22R
22R
22R
22R
22R
22R
22R
22R
22R
22R
22R
22R
22R
22R
22R
22R
22R
22R
22R
22R
22R
22R
22R
22R
22R
22R
22R
22R
22R
22R
22R
22R
22R
NC
100R
RAM & SPI FLASH
Diagram
Summary of Contents for LC-22DV510K
Page 19: ...19 LC 22DV510 LC 24DV510 1 1 General Block Diagram 1 1 General Block Diagram ...
Page 27: ...27 LC 22DV510 LC 24DV510 4 4 Frequency response ...
Page 29: ...29 LC 22DV510 LC 24DV510 5 3 Absolute Ratings 5 3 1 Electrical Characteristics ...
Page 30: ...30 LC 22DV510 LC 24DV510 5 3 2 Operating Specifications ...
Page 31: ...31 LC 22DV510 LC 24DV510 5 4 Pinning ...
Page 33: ...33 LC 22DV510 LC 24DV510 6 3 2 Operating Specifications 6 4 Pinning ...
Page 35: ...35 LC 22DV510 LC 24DV510 Ì µ µ ò Ú ĞÉîê ĞÉîé µ º ò Ú ĞÍïêô ĞÍïéô ĞÍêğ µ µ ò ...
Page 48: ...48 LC 22DV510 LC 24DV510 12 4 Pinning 11 4 ...
Page 49: ...49 LC 22DV510 LC 24DV510 ...
Page 51: ...51 LC 22DV510 LC 24DV510 ...
Page 65: ...65 LC 22DV510 LC 24DV510 23 3 VGA CN132 22 3 ...
Page 68: ...68 LC 22DV510 LC 24DV510 23 3 Options Options Options 1 Options 2 ...
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