Sharp LC-19D1E/S-BK/WH, Service Manual

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LC-19D1E/S-BK/WH
5 – 20
2.11. IC4201 (RH-iXB765WJZZ)
2.11.1 Block Diagram
2.11.2 Pin Connections and short description
256Mb DDR SDRAM
Pin No. Pin Name I/O Pin Function
45,46 CK, CK I Clock : CK and CK are differential clock inputs.
All address and control input signals are sampled on the positive edge of CK and negative edge of CK.
Output (read) data is referenced to both edges of CK.
Internal clock signals are derived from CK/CK.
44 CKE I Clock Enable : CKE HIGH activates, and CKE LOW deactivates internal clock signals, and device input
buffers and output drivers.
Taking CKE Low provides PRECHARGE POWER DOWN and SELF REFRESH operction(all bank idle)
CKE is synchronous for POWER-DOWN entry and exit, and for SELF REFRESH entry.
CKE is asynchronous for SELF REFRESH exit, and for output disable.
CKE must be maintained high throughput READ and WRITE accesses.
Input buffers, excluding CK,CK and CKE are disabled during POWER-DOWN.
Input buffers, excluding CKE are disabled during SELF REFRESH.
CKE is an SSTL_2 input, but will detect an LVCMOS Low level after Vdd is applied upon 1st power up,
After VREF has become stable during the power on and initialization sequence, it must be maintained
for proper operation of the CKE receiver.
For proper SELF-REFRESH entry and exit, VREF must be maintained to this input.
24 CS I Chip Select : CS enables(registered LOW) and disables(registered HIGH) the command decoder.
All commands are masked when CS is registered HIGH.
CS provides for external bank selection on systems with multiple banks.
CS is considered part of the command code.
21-23 RAS, CAS, WE I Command Inputs : RAS, CAS and WE (along with CS) define the command being entered.
20,47 LDM,(UDM) I Input Data Mask : DM is an input mask signal for write data.
Input data is masked when DM is sampled HIGH along with that input data during a WRITE access.
DM is sampled on both edges of DQS.
Although DM pins are input only, the DM loading matches the DQ and DQS loading.
For the x16, LDM corresponds to the data on DQ0~D7 ; UDM corresponds to the data on DQ8~DQ15.
DM may be driven high, low, or floating during READs.
26,27 BA0, BA1 I Bank Addres Inputs : BA0 and BA1 define to which bank an ACTIVE, READ,WRITE or PRECHARGE
command is being applied.