CD-XP305V
– 50 –
ICM1 VHi1625635T-1: DRAM (1625635T)
Figure 50 BLOCK DIAGRAM OF IC
1
VCC
Power supply.
2-5
D0-3
Data input/output.
6
VCC
Power supply.
7-10
D4-7
Data input/output.
11*,12*
N.C.
Not used.
13
WE_
Read/write enable.
14
RAS_
Row address strobe.
15*
N.C.
Not used.
16-19
A0-3
Address input. (ROW/REFRESH: A0 TO A3) (COLUMN: A0 TO A3)
20
VCC
POWER supply.
21
VSS
Ground
22-26
A4-8
Address input. (ROW/REFRESH: A4 TO A8) (COLUMN: A4 TO A8)
27
OE_
output enable.
28,29
CAS_,CAS2_
Column address strobe.
30*
N.C.
Not used.
31-34
D8-11
Data input/output.
35
VSS
Ground
36-39
D12-15
Data input/output.
40
VSS
Ground
Port Name
Pin No.
Function
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
RAS_
CAS2_
CAS_
WE_
A0
A1
A2
A3
A4
A5
A6
A7
A8
VCC
VSS
D0
D1
D7
D8
D9
D15
OE
Lowar
Upper
Clock generating
circuit
Lower data
Input buffer
Lower data
Output buffer
Coidmn decoder
Upper data
Input buffer
A0-A8
A0-A8
I/O control circuit
Memory cell array
Upper data
Output buffer
Roe decoder
Row and column address buffer
14
29
28
13
16
17
18
19
22
23
24
25
26
27
39
32
31
10
3
2
40
35
21
1
20
