Sharp Aquos LC 37HV6U, Service Manual

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LC-37HV6U
Ë
9DK001-15149(TLV5734PAG)(ASSY:IC10310)
TRIPLE 8-BIT 30-MSPS ADCWITH HIGH-PRECISION CLAMP FOR YUV/RGB VIDEO
»
Block Diagram
»
Pin Function
Pin No
.
Pin Name
I/O
Pin Function
1
RT A
I
Top reference voltage level for ADC A (nominal RT A _ RB A = 1 V for video signals)
2
RB A
I
Bottom reference voltage level for ADC A
3
E
XTCLP
I
External clamp pulse input (active high)
4
OEB A
I
Output enable of ADC A (active low)
5
QA DGND
—
Digital ground for output driver of ADC A
6-13
AD8-AD1
O
Data output of ADC A (MSB:AD8, LSB:AD1) (format 1, format 2, format 3)
14
QA DVDD
—
Digital supply (3.3 V) for output driver of ADC A. DVDD, QA DVDD, QB DVDD, and QC DVDD are tied together internally.
15
DGND
—
Digital ground for all logic
16
QB DVDD
—
Digital supply (3.3 V) for output driver of ADC B. DV DD , QA DV DD , QB DV DD and QC DV DD are tied together internally.
17-24
BD8-BD1
O
Data output of ADC B (MSB:BD8, LSB:BD1) (format 2) Data output of ADC B, C (format 1, format 3)
25
QB DGND
—
Digital ground for output driver of ADC B
26
DVDD
—
Digital supply (3.3 V) for all logic. DVDD, QA DVDD, QB DVDD, and QC DVDD are tied together internally.
27
OEB B
I
Output enable of ADC B (active low)
28,29
MODE1,0
I
O
utput format mode selector.
30
INIT
I
Output initialized. The output data is synchronized with the first falling edge of CLK after INIT changes from low to high (see Figure 1). INIT is a control terminal that allows the external system to initialize the TLV5734 data conversion cycle.
31
CLK
I
C
lock input. The clock frequency is four times the frequency subcarrier (fsc) for
most video systems
32
NC
—
NC should be tied low when using this device.
33
G/Y
I
Video input mode selector, low for RGB, high for YUV
34
OEB C
I
Output enable of ADC C (active low)
35
QC DVDD
—
Digital supply (3.3 V) for output driver of ADC C. DVDD, QA DVDD, QB DVDD, and QC DVDD are tied together internally.
36-43
CD8-CD1
I
Data output of ADC C (MSB:CD8, LSB:CD1) (format 2) When MODE1 = L, MODE0 = L, CD8 outputs MSB flag of BD8_BD5 (format 1) When MODE1 = L, MODE0 = L, CD7 outputs LSB flag of BD8_BD5 (format 1) When MODE1 = H, MODE0 = L, CD8 outputs B channel flag of BD8_BD1 (format 3) When MODE1 = H, MODE0 = L, CD7 outputs B channel flag of BD8_BD1 (CD8_CD1) (format 3)
44
QC DGND
—
Digital ground for output driver of ADC C
45
AGND
—
Substrate ground
46
RB C
I
Bottom reference voltage level for ADC C
47
RT C
I
Top reference voltage level for ADC C (nominal RT C _ RB C = 1 V)
48
CLP OUT C
O
Clamp bias current of ADC C. A resistor-capacitor network sets the clamp settling time.
49
CLPV C
I
Clamp level of ADC C
50
C AVCC
—
Analog supply (3.3 V) for ADC C
51
CIN
I
Analog input of ADC C. Used for R/V
52
GND C
—
Analog ground of ADC C
53
CLP OUT B
O
Clamp bias current of ADC B. A resistor-capacitor network sets the clamp settling time.
54
CLPVB
I
Clamp level of ADC B
55
B AVCC
—
Analog supply (3.3 V) for ADC B
56
BIN
I
Analog input of ADC B. Uses for B/U
57
GND B
—
Analog ground of ADC B
58
RB B
I
Bottom reference voltage level for ADC B
59
RT B
I
Top reference voltage level for ADC B (nominal RT B _ RB B = 1 V)
60
CLP OUT A
O
Clamp bias current of ADC A. A resistor-capacitor network sets the clamp settling time.
61
CLPVA
I
Clamp level of ADC A
62
A AVCC
—
Analog supply (3.3 V) for ADC A
63
AIN
I
Analog input of ADC A. Used for G/Y
64
GND A
—
Analog ground of ADC A