Sharp Aquos LC 37HV6U, Service Manual

Page: 65 / 264

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65-1
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LC-37HV6U
Ë
VH+-1Q(ASSY: IC1650)
HDCP_LSI
»
Block Diagram
Pin No
.
P
in Name
I/O
Pin Function
42
ODCK
O
Output Data Clock.
44
DE
O
Output Data Enable. This signal qualifies the active data area.
18
HSYNC
O
Horizontal Sync control signal.
19
VSYNC
O
Vertical Sync control signal.
23
IOR
O
RED Analog Out.
26
IOG
O
GREEN Analog Out.
31
IOB
O
BLUE Analog Out.
30
COMP
I
Compensation. Provides compensation for the internal reference amplifier. This pin should be connected through a 0.01_F ceramic capacitor and a 10_F tantalum capacitor to DACVCC externally. These capacitors must be as close to the pin as possible to avoid any noise pick-up.
29
RSET
I
Full Scale Adjust Resistor. A precision resistor (1%) connected between this pin and DACGND controls the magnitude of the full scale video signal. RSET may need to be adjusted for optimum gain; see page 16 for recommended values. This resistor must be as close to the pin as possible to avoid any noise pick-up.
40
SCDT
O
Sync Detect. A HIGH level is output when DE is actively toggling, indicating that the link is alive. When DE is inactive, a LOW level is output indicating the link is down. SCDT is internally connected to PD_DAC# and has the same effect as PD_DAC# driven low externally (see below). SCDT can be left unconnected, tied to PD_DAC# (redundant to internal connection), or used by an external circuit to monitor the link activity. The SCDT output remains in the active mode at all times.
20
PD_DAC#
I
DAC Power Down (active LOW). A HIGH level puts the DAC in normal operation. A LOW level powers down the DAC and puts all the video data outputs into a high impedance (tri-state) mode with a weak internal pull-down device bringing the outputs to ground. The HSYNC, VSYNC, and DE signals are not affected. Only the DAC is powered down in this mode; the chip itself is not in full power-down mode with this pin. Tie high through pullup resistor if not used.
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Pin Function
Pin No
.
P
in Name
I/O
Pin Function
11
PD#
I
Power Down (active LOW). A HIGH level puts the chip in normal operation. A LOW level puts the chip in full power down mode. During this mode the following occur: the receiver core, DAC and all analog logic are powered down; all outputs (including HSYNC, VSYNC, DE, ODCK, and data signals) are brought to logic zero (0) state. Tie high through pullup resistor if not used.
2
RX0+
Analog
Receiver Data. TMDS low voltage differential signal input data pairs.
3
RX0_
Analog
51
RX1+
Analog
52
RX1_
Analog
48
RX2+
Analog
49
RX2_
Analog
5
RXC+
Analog
Receiver Clock. TMDS low voltage differential signal input clock pair.
6
RXC_
Analog
8
EXT_RES
Analog
Impedance Matching Control. In the common case of 50_ transmission line, an external 412_ 1% resistor is recommended for connection between AVCC and this pin.
15
SCLS
I
I2C Clock. This is a slave I2C clock interface for communicating with a host side master. The clock may be run up to 400kHz. This pin is not 5V tolerant and should go through a level shifter for connection to the DDC clock line.
14
SDAS
I/O
I2C Data. This is a slave I2C data interface for communicating with a host side master. Data may be clocked in at up to 400kHz. This pin is not 5V tolerant and should go through a level shifter for connection to the DDC data line.
39
RESET#
I
Power-On Reset. This pin acts as active LOW reset for the cipher block logic. It must be held low for at least 100ns after power up. For HDCP applications, this pin should be connected to an external power-on reset circuit that causes this signal to go high after the required low period. For non-HDCP applications, this pin should always be tied LOW.
13,22,46
VCC
Power
Digital Core VCC, must be set to 3.3V.
12,21,45
GND
Ground
Digital Core GND.
17,41
OVCC
Power
Digital Output VCC, must be set to 3.3V.
16,43
OGND
Ground
Digital Output GND.
1,7
AVCC
Power
TMDS Analog VCC must be set to 3.3V.
4,47,50
AGND
Ground
TMDS Analog GND.
9
PVCC
Power
PLL Analog VCC must be set to 3.3V.
10
PGND
Ground
PLL Analog GND.
37
DACVCC
Power
DAC Analog VCC, must be set to 3.3V.
35
DACGND
Ground
DAC Analog GND.
24
DACVCCR
Power
DAC Red VCC, must be set to 3.3V.
25
DACGNDR
Ground
DAC Red GND.
27
DACVCCG
Power
DAC Green VCC, must be set to 3.3V.
28
DACGNDG
Ground
DAC Green GND.
32
DACVCCB
Power
DAC Blue VCC, must be set to 3.3V.
33
DACGNDB
Ground
DAC Blue GND.
34
No Connect
No Connect
These pins should normally be unconnected, but can be left connected to pull- ups if desired.
36
No Connect
No Connect
38
Reserved
Reserved
This pin must be tied HIGH for normal operation.