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86
27DV-S100
27DV-CS10
Refresh
Interval Timer
Refresh
Counter
Self Refresh Counter
Address
Register
Burst Length
Counter
Column Addr.
Latch & Counter
512Kx16
Bank 1
Column Decoder
Sense AMP & I/O gates
Column Decoder
Sense AMP & I/O gates
Mode Register
Test Mode
I/O Control
512Kx16
Bank 0
Row Addr. Latch/Predecode
Row Addr. Latch/Predecode
State Machine
Data Input/Output Buffers
Row Decoder
Precharge
Row Active
Column Active
Overflow
Address[0:10]
Audio/Self Refresh
Ref. Addr.[0:11]
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
CLK
CKE
BS(A11)
CS
RAS
CAS
WE
DOMU
DOML
35
CLK
Clock
The system clock input. All other inputs are referenced to the SDRAM on
the rising edge of CLK.
34
CKE
Clock Enable
Controls internal clock signal and when deactivated, the SDRAM will
be one of the states among power down, suspend or self refresh.
18
CS
Chip Select
Command input enable or mask except CLK, CKE and DOM
19
BS
Bank Address
Select either one of banks during both RAS and CAS activity.
20~24
A0~A10
Address
Row Address: RA0~RA10, Column Address: CA0~CA7
27~32
17, 16, 15
RAS, CAS, WE
Row Address Strobe,
RAS, CAS and WE define the operation.
Column Address Strobe,
Refer function truth table for details.
Write Enable
14, 36
DOML, DOMU
Data Input/Output Mask
DOM control output buffer in read mode and mask input data in write mode.
2, 3, 5,
I/O0~15
Data Input/Output
Multiplexed data input/output pin
6, 8, 9, 11, 12, 39, 40,
42, 43, 45, 46, 48, 49
VCC/VSS
Power Supply/Ground
Power supply for internal circuit and input buffer.
1, 25, 26
4, 7, 10,
VCCO/VSSO
Data Output Power/Ground Power supply for DO
13, 38, 41, 44, 47, 50
33, 37
NC
No Connection
No connection
IC602-3 IX3455CE 16M SDRAM
Pin No.
Terminal Name
Name
Input Function
• Block Diagram
Summary of Contents for 27DV-CS10
Page 72: ...73 27DV S100 27DV CS10 72 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H CHASSIS LAYOUT ...
Page 103: ...111 27DV S100 27DV CS10 6 5 4 3 2 1 A B C D E F G H SCHEMATIC DIAGRAM CRT Unit ...
Page 106: ...116 27DV S100 27DV CS10 6 5 4 3 2 1 A B C D E F G H SCHEMATIC DIAGRAM TERMINAL SUB Unit ...
Page 107: ...117 27DV S100 27DV CS10 6 5 4 3 2 1 A B C D E F G H SCHEMATIC DIAGRAM FRONT AV Unit ...
Page 122: ...144 27DV S100 27DV CS10 6 5 4 3 2 1 A B C D E F G H MAIN Unit Wiring Side ...
Page 123: ...145 27DV S100 27DV CS10 6 5 4 3 2 1 A B C D E F G H MAIN Unit Chip Parts Side ...
Page 124: ...146 27DV S100 27DV CS10 6 5 4 3 2 1 A B C D E F G H TERMINAL Unit Wiring Side ...
Page 125: ...147 27DV S100 27DV CS10 6 5 4 3 2 1 A B C D E F G H TERMINAL Unit Chip Parts Side ...
Page 126: ...148 27DV S100 27DV CS10 6 5 4 3 2 1 A B C D E F G H TV POWER Unit Wiring Side ...
Page 127: ...149 27DV S100 27DV CS10 6 5 4 3 2 1 A B C D E F G H DEFLECTION Unit Wiring Side ...
Page 128: ...150 27DV S100 27DV CS10 6 5 4 3 2 1 A B C D E F G H DVD VCR POWER Unit Wiring Side ...
Page 130: ...152 27DV S100 27DV CS10 6 5 4 3 2 1 A B C D E F G H DVD MAIN Unit A Side ...
Page 131: ...153 27DV S100 27DV CS10 6 5 4 3 2 1 A B C D E F G H DVD MAIN Unit B Side ...