SGS TS68483A Manual Download Page 5

of lines per field (up to 1024). The address of the
display viewport (this part of the display memory to
be actually displayed on the screen) is fully pro-
grammable. The display processor provides the
display dynamic RAM refresh (see video timing
generator section for details).

I.3.2 - DRAWING AND ACCESS COMMANDS (R0
to R3, R12 to R23).

The 16 remaining registers are used to specify a
comprehensive set of commands. The highly or-
thogonal drawing command set allows the user to
”draw” in the display memory such basic patterns
as lines, arcs, polylines, polyarcs, rectangles and
characters. Efficient procedures are available for
either area filling and tiling or line drawing and
texturing. Lines may be drawn with a PEN in order
to get thick strokes. Any drawing is specified in a
2

13

x 2

13

drawing coordinate system.

To access the display memory, the host microproc-
essor has an indirect, sequential access to any
”window”. Access commands can be used to load
the character generators as well as to load or save
arbitrary windows stored in the frame buffer.

I.4 - Data Type Definitions

PIXEL : this is the smallest color spot displayable
on the CRT.

PEL : a Picture Element is the coding of a PIXEL in
the display memory. The TS68483 can handle 4
different PEL formats :
- 4 color bits - short
- 4 color bits + 1 mask bit - short masked
- 8 color bits - long
- 8 color bits + 1 mask bit - long masked

DRAWING COORDINATES : (see Figure 2)
The drawing commands are specified and com-
puted in a 2

13

x 2

13

cyclical coordinate system. The

drawing coordinates are clipped and mapped into
the 2

11

x 2

11

display memory addressing space.

Further clipping to the actual frame buffer size may
be performed by the user designed memory inter-
face.

DISPLAY MEMORY :
This is the dedicated memory to the display unit.
This memory is addressed as four banks of 4-bit
plane each.

BIT PLANE :
Each bit plane has a maximum capacity of 2

11

x 2

11

bits. A byte wide organization of each bit plane is
required.

MEMORY ADDRESS : (see Figure 3).
In order to address one bit in the display memory,
the user must specify :
- A bank number (2 bits) B = 0 to 3
- A bit plane number (2 bits) Z = 0 to 3
- A Y address (11 bits) Y = 0 to 2047
- An X address (11 bits) X = 0 to 2047
MEMORY WORD : (see Figure 3)
A 32-bit memory word can be either read or written
during each memory cycle (8 CLK periods), one
byte at a time in each bit plane in the addressed
bank. The memory bandwidth is in the 6 to 8Mby-
tes/s range.
VIEWPORT :
This is any rectangular array of pels located in the
display memory.

FRAME BUFFER :
This is the biggest viewport which can be held in
the display memory. The frame buffer maps a
window at the origin of the drawing coordinates. A
short pel frame buffer may be located in any bank.
A long pel frame buffer must be located in the ”bank
0, bank 1” pair.

DISPLAY VIEWPORT :
This is the viewport which is displayed on screen.

MASK BIT PLANE :
When masked pels are used, a mask bit plane must
be associated to a frame buffer. Mask bit planes
may be located in any plane of bank 3.

CELL :
A CELL is any pattern stored in the display memory
as a rectangular array of bit mapped elements. The
drawing of any CELL may be specified with a
scaling factor.
CHARACTER :
This is a one bit per element CELL. It may be stored
in any bit plane, then colored and drawn in a frame
buffer by use of PRINT CHARACTER command.
OBJECT :
This is a one short pel per element CELL. It may
be drawn or loaded in a frame buffer.A source mask
bit may be associated to each element. An OB-
JECT may then be printed in another location by
use of a PRINT OBJECT command.

PEN :
This is the pattern which is repeatedly drawn along
the coordinates defined by either a LINE or an ARC
command.

The PEN may be a DOT (single pel), a CHARAC-
TER or an OBJECT.

TS68483A

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Summary of Contents for TS68483A

Page 1: ...OR PEN CONCEPT AND PROGRAMMABLE LINE STYLE FLEXIBLE AREA FILL COMMAND WITH TILING PATTERN VERY FAST BLOCK MOVE OPERATION CHARACTER DRAWING COMMAND ANY SIZE AND FONTS AVAILABLE LARGE FRAME BUFFER ADDR...

Page 2: ...onnected to the WR signal CS I Chip Select This input selects the TS68483 registers for the current bus cycle A low level corresponds to an asserted chip select In multiplexed mode this input is strob...

Page 3: ...Voltage 0 3 7 0 V Vin Input Voltage 0 3 7 0 V TA Operating Temperature Range 0 70 C Tstg Storage Temperature Range 55 150 C PDm Max Power Dissipation 1 5 W 68483 02 TBL With respect to VSS Stresses a...

Page 4: ...CRT monitor The display unit consists of four hardware building blocks an TS68483 advanced graphics controller a display memory dynamic RAM a displaymemoryinterface comprising a fewTTL parts a CRT int...

Page 5: ...lay unit This memory is addressed as four banks of 4 bit plane each BIT PLANE Each bit plane has a maximum capacityof 211 x 211 bits A byte wide organization of each bit plane is required MEMORY ADDRE...

Page 6: ...a given type For example any drawing command may be parame tered for destination mask bit use The command code also defines the command type and its parameters A command is completely defined when a v...

Page 7: ...not specified Xs 0 to 255 a cell dimension DXs DYs a bit plane address Zs When a character is addressed Zs gives the plane number into the bank Bs When an object is ad dressed Zs gives the source mask...

Page 8: ...R22 R23 15 14 13 12 11 10 9 8 7 6 4 5 3 2 1 0 13 bit positive value Bank number Plane number 13 bit positive value Absolute value Absolute value 11 bit positive value 8 bit positive value Absolute va...

Page 9: ...nerally addressed as the frame buffer When short pels are used any bank may hold a frame buffer In thiscase the bankparity selectsthe color nibble used See destination pointer section for bank address...

Page 10: ...he penis a CELL this cell is printed at each active coordinate In the bichrome mode when the cell is a character and in the polychrome mode when the cell is an object For each active coordinates the a...

Page 11: ...the PRINT CHARACTER PRINT OBJECT and LIN EAR commands when the pen is a cell The AREA or ACCESS or LINEAR DOT commands are never scaled The LINEAR PEN command should be used with a scaling factor of...

Page 12: ...DXs DYs SAVE VIEWPORT Xs Ys DXs DYs MODIFY VIEWPORT Xs Ys DXs DYs These commands provide sequential access to a viewport in a frame buffer from the microprocessor data base Data are transferred to fr...

Page 13: ...4 registers A0 selects the low order byte A0 1 or the high order byte A0 0 of the selected register A 6 7 provide the command execution condition The host microprocessor bus may be either 8 or 16 bits...

Page 14: ...D 8 15 TS68483 TS68008 V CS R W DS CC 68483 16 EPS Figure 14 Interface with TS68000 68008MPU 37 26 28 25 29 AD 8 15 AD 0 7 A 1 7 D 0 7 D 8 15 TS68483 8086 ALE CS WR 26 28 25 29 AD 0 7 A 1 7 D 0 7 D 8...

Page 15: ...Word 1 Long Word 1 1 Exec after 4 Bus Cycles 1 Long Word ILLEGAL Notes Word transfer must respect word boundary Long word transfer must respect long word boundary Not available with 8088 MPU type 684...

Page 16: ...d to load the internal video RAM shift register the non displayable lines In one out of nine non displayablelines DWX cyclesare allocatedto the refresh process when it is enabled RFD 0 In Float cycle...

Page 17: ...must be programmed to use external shift register Dummy read IV 3 4 PAN AND TILT The host can tilt or pan the Display Viewport through the frame bufferby modifying YOR or XOR arguments Panning isperfo...

Page 18: ...the bank number X 3 10 binary value of the word address Y 0 10 binary value of the word address Z and X 0 2 are not supplied They give only a bit address in a memory word V 2 Memory Cycles 24 pins are...

Page 19: ...onging to different banks but addressed by the same Z share a given block There is little time constraint if any One block twoZ two bit planes belongingto the same bank share a given block In this cas...

Page 20: ...in bank3 V 3 3 OBJECTS AND CHARACTERS Objects may be located in unused parts of the frame buffer Character generators can be implemented in any plane of any bank They can also be implemented in ROM In...

Page 21: ...rocessors UNMUX MODE Microprocessor Interface Timing A 0 7 D 0 15 AE DS CS R W VCC 5 0V 5 TA TL to TH CL 100pF on D 0 15 Reference levels VIL 0 8V and VIH 2V on all inputs VOL 0 4V and VOH 2 4V on all...

Page 22: ...6 7 8 1 5 3 2 4 A 0 7 AS MPU CS DS R W DATA OUT D 0 15 68483 23 EPS Figure 21 Read Cycle 3 8 1 5 3 2 A 0 7 AS MPU CS DS R W DATA IN D 0 15 10 9 11 12 68483 24 EPS Figure 22 Write Cycle TS68483A 22 30...

Page 23: ...and R W High 150 ns 6 DS Width low read 240 ns 7 R W Width low write 110 ns 8 Data Access Time From DS read 210 ns 9 Data in Set up time from R W Inactive write 150 ns 10 DS Inactive to High Impedance...

Page 24: ...3 3 16 5 8 10 14 12 A D OUT AE CS DS R W A D 6 68483 25 EPS Figure 23 Read Cycle 1 2 4 3 3 A AE CS DS R W A D 17 5 13 15 A DIN DIN 18 9 11 11 7 FAST WRITE 68483 26 EPS Figure 24 Write Cycle TS68483A...

Page 25: ...LK 10 ns 6 Input Data Hold Time from CLK read cycle 6 ns 7 Input Data Set up Time from CLK read cycle 10 ns 8 Input Data HI Z Time from CLK TCLK ns Note All timing is referenced to the rising edge of...

Page 26: ...from CLK Rising Edge 30 ns 4 CLK Low Pulse Width 23 ns 5 Output Hold Time 10 ns 68483 14 TBL 2HT 7T 7T 1T 2T MARGIN MARGIN DWX FPX BKX 25LINES 25LINES 25LINES 25LINES EVEN FIELD BKY FPY DWY BPY LINES...

Page 27: ...en Bank 0 DIB1 DIB0 MARGIN COLOR YOR XOR H BFY FPY BKY DPD VRE RFD INE BKX DWX FPX 0 MODX1 MODX0 BW MB VSIE HSIE NBLK NHVS NPC STATUS SYNC DWY DY S S DX Bd Zd S S ACW XY QF1 QF0 Bs Zs S U DXs DYs Xs Y...

Page 28: ...CELL 10T LOOP 4T CELL 4T 10T 4T 4T see Note 1 6T 5T 4T 10T AREA MEMORY WORD EXECUTIONTIME Per DOT CELL DOT CELL MEMORY WORD MEMORY WORD DMU 1 Destination mask use SP 1 Short pel long pel when SP 0 SRU...

Page 29: ...TEM MEMORY HOST MICROPROCESSOR DISPLAY MEMORY DISPLAYMEMORY INTERFACE TS68483 CRT CONTROLLER 4 SYNC SYNC R G B CRT INTERFACE MONITOR 8 OR 16 BITS 68483 32 EPS Figure 29 Typical Application TS68483A 29...

Page 30: ...re not authorized for use as critical components in life support devices or systems without express written approval of SGS THOMSON Microelectronics 1994 SGS THOMSON Microelectronics All Rights Reserv...

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