Table 4
Name
Number
of Bits
Mininmum
Values
Register
Description
Function
DWY
10
1
R9
Number of Display lines per Field
Vertical
Scan
INE
1
R8
Interlace Enable when INE = 1
BKY
5
1
R8
Number of Lines in Vertical Blanking – 2.5
FPY
5
1
R7
Number of Lines in Vertical Front Porch
BPY
8
3
R6
Number of Lines in Vertical Back Porch + 2.5
H
6
19
R6
Number of Double Cycles per Line
Horizontal
Scan
FPX
4
3
R8
Number of Cycles in Horizontal Front Porch
BKX
4
4
R8
Number of Cycles in Horizontal Blanking – 3
DWX
7
3
R7
Number of Cycles of the Display Window
XOR
8
R4
X, Y, and bank logical address in the display
memory of the display viewport upper left corner
Display
Process
YOR
11
R5
DIB
2
R4
MODX
2
R9
Selection of the X Addressing Mode
MC
4
R4
Margin Color
RFD
1
R7
RAM Refresh Disable when RFD = 1
Memory
Time
Sharing
DPD
1
R7
Display Process Disable when DPD = 1
VRE
1
R8
Video RAM Enable When VRE = 1
Note : one cycle = 8 periods of CLK Clock
68483-07.TBL
V. MEMORY ORGANIZATION
V.1 - Introduction
The display memory is logically organized as four
banks of 4-bit planes. Thus a bit address in the
display memory is given by the quadruplet :
- B = bank number, from 0 to 3
- Z = plane number, from 0 to 3
- X = bit address into the plane, from 0 to 2047
- Y = bit address into the plane, from 0 to 2047.
In one memory cycle (8 CLK periods), the controller
can access a memory word. This 32-bit memory
word holds one byte from each plane in a given
bank. In order to address this memory word, the
controller supplies :
- B(0:1) : binary value of the bank number
- X(3:10) : binary value of the word address
- Y(0:10) : binary value of the word address.
Z and X(0:2) are not supplied. They give only a bit
address in a memory word.
V.2 - Memory Cycles
24 pins are dedicated to the memory interface.
- ADM(0:15) : these 16 bidirectional pins are mul-
tiplexed three times during a memory cycle (see
Figure 25) :
TA
: address period. Output of the X(3:11)
and Y(3:11) address
TO
: even data period. The even Z bytes are
either input or output.
T1
: odd data period. The odd Z bytes are
either input or output.
Y(0:2) : three LSB Y address output pins (non-
multiplexed)
B(0:1) : two bank address output pins (non-
multiplexed)
- CYS : Cycle start strobe output (non-multiplexed).
CYS is at CLK/8 frequency. A CYS pulse is deliv-
ered only when a command, display or refresh
cycle is performed.
- CYF(0:1) : Two cycle status outputs (non-multi-
plexed). Four cycle types are defined : Command
Read, Command Write, RAM Refresh, Display
Access.
Because several options may be selected for RAM
refresh and display access by the MODX and VRE
flags (see Video Timing Section), there are more
than four memory cycle types (see Figure 25 and
Table 5).
V.3 - Display Memory Desing Overview
The display memory implementation is application
dependant. The basic parameters are :
- the number of pixels to be displayed Nx.Ny
- the number of bits per pel
- the vertical scanning frequency, which must be
picked in the 40Hz to 80Hz range (non interlaced)
or in the 60Hz to 80Hz range (interlaced).
This yields a rough estimate of the pixel frequency.
When the pixel frequency is in the 15 to 18MHz
range and 4 bits per pixel or least are required, the
on-chip video registers and standard dynamic RAM
components may be used. When higher pixel rates
TS68483A
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