μ
Q7-962
μ
Q7-962 User Manual - Rev. First Edition: 1.0 - Last Edition: 3.1 - Author: S.B. - Reviewed by P.Z Copyright © 2016 SECO S.r.l.
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3.2.1.1
PCI Express interface signals
The μ
Q7-962 module can offer one PCI Express lane, which is directly managed by i.MX6 processor (all versions).
PCI express Gen 2.0 (5Gbps) is supported. Of the previous generation, only PCI express 1.1 is supported.
Here following the signals involved in PCI express management
P/PCIE0_TX-: PCI Express lane #0, Transmitting Output Differential pair
P/PCIE0_RX-: PCI Express lane #0, Receiving Input Differential pair
PCIE_/ PCIE_CLK_REF-: PCI Express Reference Clock for lane #0, Differential Pair
PCIE_WAKE#: Qseven
®
Module
’
s Wake Input, it must be externally driven by devices requiring waking up the system. Since it is an Active-Low Input to the
module, this signal is pulled-up with a 10k
Ω
resistor to +3.3V_A power rail. On the carrier board, connect it directly to the PCI-e/miniPCI-e connector
’
s WAKE#
signal, or to WAKE# signal of any eventual PCI-e Controller present on the Carrier Board.
PCIE_RST#: Reset Signal that is sent from Qseven
®
Module to any PCI-e device available on the carrier board. It is a 3.3V active-low signal, tied to GND via a
47k
Ω
resistor; it can be used directly to drive externally a single RESET Signal. In case Reset signal is needed for multiple devices, it is necessary to provide for a
buffer on the carrier board.
