
CCOMe-C96
CCOMe-C96 - Rev. First Edition: 1.0 - Last Edition: 1.0 - Author: A.R. - Reviewed by C.M. Copyright © 2021 SECO S.p.A.
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PEG (PCI Express Graphics x16) Connector
According to COM Express specifications, it is possible to expand the graphical capabilities of the board by using the
dedicated PCI Express Graphics x16 bus (PEG) interface, which can be accessed through a card edge connector type
LOTES p/n APCI0470-P002C or equivalent, with the pinout shown in the following table.
Please check the User Manual of the COM Express module used for details about the availability of these lanes.
Please be aware that availability of these PCI express lanes depends on the COM Express module used.
Please check the User Manual of the COM Express module used for details about the availability of these lanes and all possible groupings that can be applied to
these lanes.
PCI Express Graphics x16 Slot- CN13
Description
Pin name
Pin nr.
Pin nr.
Pin name
Description
+12V Power Rail
+12V_RUN
B1
A1
GND
Hot Plug presence detect (tied to GND)
+12V Power Rail
+12V_RUN
B2
A2
+12V_RUN
+12V Power Rail
+12V Power Rail
+12V_RUN
B3
A3
+12V_RUN
+12V Power Rail
Power Ground
GND
B4
A4
GND
Power Ground
SM Bus Clock line. +3.3V_RUN electrical level with
up resistor, derived by SMB_CK with
mosfet voltage level converter
PCIE_ SMB_CLK
B5
A5
JTAG2
TCK, tied to GND with 4K7
Ω
resistor
SM Bus Data line. +3.3V_RUN electrical level with
up resistor, derived by SMB_DAT with
mosfet voltage level converter
PCIE_ SMB_DAT
B6
A6
JTAG3
TDI, tied to +3.3V_RUN with 4K7
Ω
resistor
Power Ground
GND
B7
A7
JTAG4
Test Data Out, not connected
+3.3V Power Rail
+3.3V_RUN
B8
A8
JTAG5
TMS, tied to +3.3V_RUN with 4K7
Ω
resistor
TRST#, tied to GND with 4K7
Ω
resistor
JTAG1
B9
A9
+3.3V_RUN
+3.3V Power Rail
+3.3V Auxiliary Power Rail
+3.3V_ALW
B10
A10
+3.3V_RUN
+3.3V Power Rail
Wake signal for link reactivation
WAKE0#
B11
A11
PEG_RST#
Reset signal to the add-in card, derived by
CB_RESET# using a Ultra High Speed CMOS
buffer. Active low signal, +3.3V_ALW electrical level
with a 100k
Not Connected
RSVD
B12
A12
GND
Power Ground
Power Ground
GND
B13
A13
PCI-e reference clock lane +, derived by
PCIE using a Clock Buffer