CCOMe-C79
CCOMe-C79 - Rev. First Edition: 1.0 - Last Edition: 1.0 - Author: A.R. - Reviewed by E.S. Copyright © 2021 SECO S.p.A.
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10G_PHY_MDC_OCP_SCL: Management Data I/O Interface mode (MDIO mode) or I2C (I2C mode) clock signal for serial data transfers between the MAC and an
external PHY. Its routing to OCP connector is controlled by JP11 to select which I2C/MDIO lane is selected, and its capability mode (MDIO-only or MDIO/I2C) is
regulated by JP12 (PHI lane#2 and#3) and JP13 (PHI lane#0 and#1)
10G_PHY_MDC_OCP_SDA: Management Data I/O Interface mode (MDIO mode) or I2C (I2C mode) data signal for serial data transfers between the MAC and an
external PHY. Its routing to OCP connector is controlled by JP11 to select which I2C/MDIO lane is selected, and its operating mode (MDIO-only or MDIO/I2C) is
regulated by JP12 (PHI lane#2 and#3) and JP13 (PHI lane#0 and#1)
+VIN_OCP: Power for external OCP module. It will be +5V_ALW when the module is turned off, while +12V_RUN when is turned on
In addition, the MDIO/I2C signals from COM Express
™
module are available
on a dual row 10 pin, P2.54mm standard pin header 10-pin header, type
ADIMPEX p/n LE008210-R or equivalent.
#49 and #50. Switching is controlled via Jumper JP11.
Four on-board yellow LEDs D53-D56 notify that maximum link speed of the corresponding
10Gb Ethernet ports has been reached (D53 for PHI #0 and so on).
Signals Description:
10G_PHY_MDIO_SDA[0:3]: Management Data I/O Interface mode (MDIO mode) or I2C (I2C mode) data signal for serial data transfers between the MAC and an
external PHY
10G_PHY_MDC_SCL[0:3]: Management Data I/O Interface mode (MDIO mode) or I2C (I2C mode) clock signal for serial data transfers between the MAC and an
external PHY
The MC79 carrier board offers four Software Definable Pin (SDP) interfaces, supporting both input and output operation, according to COM Express Rel. 3.0
specifications. The SDP can be used to provide a timing communication path between the Module and Carrier.
A board level signal that communicates time is a key element that facilitates clock synchronization between elements of a platform.
These interfaces are available on as many SMA RF connectors CN53 (10G_SDP0), CN54 (10G_SDP2), CN55 (10G_SDP1), CN56 (10G_SDP3) , type Amphenol
p/n 132134.
MDIO / I2C Connector - CN60
Pin Signal
Pin
Signal
1
10G_PHY_MDC_SCL2
2
10G_PHY_MDC_SCL0
3
10G_PHY_MDIO_SDA2
4
10G_PHY_MDIO_SDA0
5
10G_PHY_MDC_SCL3
6
10G_PHY_MDC_SCL1
7
10G_PHY_MDIO_SDA3
8
10G_PHY_MDIO_SDA1
9
GND
10
GND
