CCOMe-C79
CCOMe-C79 - Rev. First Edition: 1.0 - Last Edition: 1.0 - Author: A.R. - Reviewed by E.S. Copyright © 2021 SECO S.p.A.
37
10k
Power Ground
GND
B32
A32
RSVD
Not Connected
PCI-e x 4 Slot CN14
Description
Pin name
Pin nr.
Pin nr.
Pin name
Description
+12V Power Rail
+12V_RUN
B1
A1
PRSNT1#
Hot Plug presence detect (tied to GND)
+12V Power Rail
+12V_RUN
B2
A2
+12V_RUN
+12V Power Rail
+12V Power Rail
+12V_RUN
B3
A3
+12V_RUN
+12V Power Rail
Power Ground
GND
B4
A4
GND
Power Ground
SM Bus Clock line. +3.3V_RUN electrical level with
up resistor, derived by SMB_CK with
mosfet voltage level converter
PCIE_ SMB_CLK
B5
A5
JTAG2
Not connected
SM Bus Data line. +3.3V_RUN electrical level with
up resistor, derived by SMB_DAT with
mosfet voltage level converter
PCIE_ SMB_DAT
B6
A6
JTAG3
Not connected
Power Ground
GND
B7
A7
JTAG4
Not connected
+3.3V Power Rail
+3.3V_RUN
B8
A8
JTAG5
Not connected
Not Connected
JTAG1
B9
A9
+3.3V_RUN
+3.3V Power Rail
+3.3V Auxiliary Power Rail
+3.3V_ALW
B10
A10
+3.3V_RUN
+3.3V Power Rail
Wake signal for link reactivation
WAKE0#
B11
A11
PCIEx4_2_RST#
Reset signal to the add-in card, derived by
CB_RESET# using a Ultra High Speed CMOS
buffer. Active low signal, +3.3V_ALW electrical level
with a 100k
Not Connected
RSVD
B12
A12
GND
Power Ground
Power Ground
GND
B13
A13
PCIEx4_2_CLK_P
PCI-e reference clock lane +, derived by
PCIE using a Clock Buffer
PCI-e Transmitter lane 4+
P
B14
A14
PCIEx4_2_CLK_N
PCI-e reference clock lane +, derived by
PCIE_CK_REF- using a Clock Buffer
PCI-e Transmitter lane 4-
PCIE_TX4-
B15
A15
GND
Power Ground
Power Ground
GND
B16
A16
P
PCI-e Receiver lane 4+
Hot Plug presence detect. Input Signal from add in
card used to enable the reference clock of this slot.
Active low signal, +3.3V_RUN electrical level with a
10k
PRSNT2#
B17
A17
PCIE_RX4-
PCI-e Receiver lane 4-
