Seanix Kootenay, User Manual

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EDO Read Burst Timing - This option specifies the timings for EDO DRAM system
memory for Read operations in burst mode. The settings are x222 or x333. The
Optimal default setting is x222.
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EDO Write Burst Timing - This option specifies the timings for EDO DRAM system
memory for Write operations in burst mode. The settings are x222 or x333. The
Optimal default setting is x222.
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EDO RAS Precharge - This option specifies the length of the RAS precharge part of
the DRAM system memory access cycle when EDO DRAM system memory is
installed in this computer. The settings are 3 CLKs or 4 CLKs. The default setting is
3 CLKs.
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EDO RAS To CAS - This option specifies the length of the delay inserted between
the RAS and CAS signals of the DRAM system memory access cycle when EDO
DRAM system memory is installed in this computer. The settings are 2 CLKs or 3
CLKs. The default setting is 3 CLKs.
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MA Wait State - This option specifies the length of the delay inserted between MA
signals. The settings are Slow or Fast. The Optimal and Fail-Safe default settings
are Slow.
SDRAM Timing Latency –
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RAS To CAS This option specifies the length of the delay inserted between the
RAS and CAS signals of the DRAM system memory access cycle. The settings are
2 CLKs or 3 CLKs. The Optimal default setting is 2 CLKs.
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CAS Lattency.- This option sets the latency period for the CAS signal. The settings
are 2 CLKs or 3 CLKs. The Optimal and Fail-Safe default settings are 3 CLKs.
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RAS Precharge Time - This option specifies the length of the RAS precharge part of
the DRAM system memory access cycle when EDO DRAM system memory is
installed in this computer. The settings are 3 CLKs or 2 CLKs. The Optimal default
setting is 2 CLKs.
DRAM Integrity Mode
This option sets the type of system memory checking. The settings are:
Setting Description
Non ECC No error checking or error reporting is done.
ECC Only Multibit errors are detected and reported as parity errors. Single-
bit errors are corrected by the chipset. Corrected bits of data from
memory are not written back to DRAM system memory. If Level I
is selected, the J25 External SMI software jumper on the Series
745 board is disabled.
ECC Multibit errors are detected and reported as parity errors. Single-
bit errors are corrected by the chipset and are written back to
DRAM system memory. If a soft (correctable) memory error
occurs, writing the fixed data back to DRAM system memory will