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Serial ATA Native Command Queuing 

Native Command Queuing achieves high performance and efficiency through efficient command 
re-ordering.  In addition, there are three new capabilities that are built into the Serial ATA protocol 
to enhance NCQ performance including race-free status return, interrupt aggregation, and First 
Party DMA.   

 

  Race-Free Status Return Mechanism 

This feature allows status to be communicated about any command at any time. There is no 
“handshake” required with the host for this status return to take place.  The drive may issue 
command completions for multiple commands back-to-back or even at the same time. 

 

 Interrupt 

Aggregation 

Generally, the drive interrupts the host each time it completes a command.  The more interrupts, 
the bigger the host processing burden.  However, with NCQ, the average number of interrupts per 
command can be less than one.  If the drive completes multiple commands in a short time span – 
a frequent occurrence with a highly queued workload – the individual interrupts may be 
aggregated.  In that case, the host controller only has to process one interrupt for multiple 
commands. 

 

  First Party DMA (FPDMA) 

Native Command Queuing has a mechanism that lets the drive set up the Direct Memory Access 
(DMA) operation for a data transfer without host software intervention.  This mechanism is called 
First Party DMA.  The drive selects the DMA context by sending a DMA Setup FIS (Frame 
Information Structure) to the host controller.  This FIS specifies the tag of the command for which 
the DMA is being set up.  Based on the tag value, the host controller will load the PRD table 
pointer for that command into the DMA engine, and the transfer can proceed without any software 
intervention.  This is the means by which the drive can effectively re-order commands since it can 
select the buffer to transfer on its own initiative. 

Detailed Description of NCQ 

There are three main components to Native Command Queuing: 

1.  Building a queue of commands in the drive 

2.  Transferring data for each command 

3.  Returning status for the commands that were completed 

The following sections will detail how each mechanism works. 

Building a Queue 

The drive must know when it receives a particular command whether it should queue the 
command or whether it should execute that command immediately.  In addition, the drive must 
understand the protocol to use for a received command; the command protocol could be NCQ, 
DMA, PIO, etc.  The drive determines this information by the particular command opcode that is 
issued.  Therefore in order to take advantage of NCQ, commands that are specifically for NCQ 
were defined.  There are two NCQ commands that were added as part of the NCQ definition in 
Serial ATA II, Read FPDMA Queued and Write FPDMA Queued.  The Read FPDMA Queued 
command inputs are shown in Figure 1; the inputs for Write FPDMA Queued are similar.  The 
commands are extended LBA and sector count commands to accommodate the large capacities 
in today’s drives.   

 

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Summary of Contents for ST3250620AS - Barracuda 250GB 7200 RPM 16MB Cache SATA 3.0Gb/s Perpendicular Recording Hard Drive

Page 1: ...July 2003 Serial ATA Native Command Queuing An Exciting New Performance Feature for Serial ATA A JOINT WHITEPAPER BY Intel Corporation and Seagate Technology www intel com www seagate com...

Page 2: ...mands to be outstanding within a drive at the same time Drives that support NCQ have an internal queue where outstanding commands can be dynamically rescheduled or re ordered along with the necessary...

Page 3: ...onal Position Ordering to optimally re order commands to maximize performance Seek Latency Optimization Seek latencies are caused by the time it takes the read write head to position and settle over t...

Page 4: ...ve almost simultaneously Higher RPM spindles are one approach to reduce rotational latencies However increasing RPM spindle rates carries a substantial additional cost Rotational latencies can also be...

Page 5: ...nding a DMA Setup FIS Frame Information Structure to the host controller This FIS specifies the tag of the command for which the DMA is being set up Based on the tag value the host controller will loa...

Page 6: ...s written with the particular register values and then the Command register is written with the command opcode The difference between queued and non queued commands is what happens after the command i...

Page 7: ...alled Auto Activate which can eliminate one FIS transfer during a write command One important note for HBA designers is that new commands cannot be issued between the DMA Setup FIS and the completion...

Page 8: ...the drive can return a Set Device Bits FIS without a host handshake it is possible to receive two Set Device Bits FISes very close together in time If the second Set Device Bits FIS arrives before hos...

Page 9: ...ointer to buffer to place data in 1024 Want to read 1024 bytes from the file numBytesRead Number of bytes read from the file NULL Synchronous so overlapped parameter is NULL Code for checking the stat...

Page 10: ...50 Wait up to 50 milliseconds for completion could be infinity Check the value of dwResult and also call GetOverlappedResult to ensure that each IO that completed was with good status As can be seen...

Page 11: ...ntroller Interface AHCI definition Amber holds a BSE in Computer Engineering from the University of Michigan and has been with Intel for 6 years Joni Clark Product Marketing Manager Seagate Technology...

Page 12: ...Serial ATA Native Command Queuing 12...

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